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MF1167-02
LCD Controller ICs
S1D13305 Series
Technical Manual
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. V In this manual, Zilog's Z80-CPU or its equivalent shall be called Z80, Intel's 8085A or its equivalent shall be called 8085 and Motorola's MC6809 and MC6802 or their equivalents shall be called 6809 and 6802, respectively. (R) stands for registered trade mark. All other product names mentioned herein are trademarks and/or registered trademarks of their respective owners. (c) Seiko Epson Corporation 2001 All rights reserved.
The information of the product number change
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.
Configuration of product number
Devices
S1 D 13706 F 00A0 00
Packing specification Specification Package (B: CSP, F: QFP) Corresponding model number Model name (D: driver, digital products) Product classification (S1: semiconductor)
Evaluation Board
S5U 13705 P00C
Specification Corresponding model number (13705: for S1D13705) Product classification (S5U: development tool for semiconductor)
Comparison table between new and previous number
* S1D13305 Series Previous No.
SED1335 Series SED1335D0A SED1335F0A SED1335F0B
* S1D1370x Series New No. Previous No.
SED137x Series SED1374F0A SED1375F0A SED1376B0A SED1376F0A
* S1D1380x Series New No. Previous No.
SED138x Series SED1386F0A
New No.
S1D1380x Series S1D13806F00A
S1D13305 Series S1D13305D00A S1D13305F00A S1D13305F00B
S1D1370x Series S1D13704F00A S1D13705F00A S1D13706B00A S1D13706F00A S1D13708 Series
* S1D1350x Series Previous No.
SED135x Series SED1353D0A SED1353F0A SED1353F1A SED1354F0A SED1354F1A SED1354F2A SED1355F0A SED1356F0A
New No.
S1D1350x Series S1D13503D00A S1D13503F00A S1D13503F01A S1D13504F00A S1D13504F01A S1D13504F02A S1D13505F00A S1D13506F00A
SED1378 Series
* S1D13A0x Series Previous No.
SED13Ax Series SED13A3F0A SED13A3B0B SED13A4B0B
New No.
S1D13A0x Series S1D13A03F00A S1D13A03B00B S1D13A04B00B
Comparison table between new and previous number of Evaluation Boards
* S1D1350x Series Previous No.
SDU1353#0C SDU1354#0C SDU1355#0C SDU1356#0C
* S1D1370x Series New No. Previous No.
SDU1374#0C SDU1375#0C SDU1376#0C SDU1376BVR SDU1378#0C
* S1D1380x Series New No. Previous No.
SDU1386#0C
New No.
S5U13806P00C
S5U13503P00C S5U13504P00C S5U13505P00C S5U13506P00C
S5U13704P00C S5U13705P00C S5U13706P00C S5U13706B32R S5U13708P00C
* S1D13A0x Series Previous No.
SDU13A3#0C SDU13A4#0C
New No.
S5U13A03P00C S5U13A04P00C
CONTENTS
CONTENTS
1. OVERVIEW ................................................................................................................................................................. 1 2. FEATURES ................................................................................................................................................................. 1 3. BLOCK DIAGRAM ....................................................................................................................................................... 2 4. PINOUTS ..................................................................................................................................................................... 3 5. PIN DESCRIPTION ..................................................................................................................................................... 4 5.1. S1D13305F00A/00B Pin Summary ................................................................................................................... 4 5.2. Pin Functions ..................................................................................................................................................... 5 5.2.1. Power supply ......................................................................................................................................... 5 5.2.2. Oscillator ................................................................................................................................................ 5 5.2.3. Microprocessor interface ........................................................................................................................ 5 5.2.4. Display memory control ......................................................................................................................... 6 5.2.5. LCD drive signals ................................................................................................................................... 7 6. SPECIFICATIONS ....................................................................................................................................................... 7 6.1. Absolute Maximum Ratings ............................................................................................................................... 7 6.2. S1D13305 .......................................................................................................................................................... 8 6.3. S1D13305F Timing Diagrams .......................................................................................................................... 10 6.3.1. 8080 family interface timing ................................................................................................................. 10 6.3.2. 6800 family interface timing ................................................................................................................. 11 6.3.3. Display memory read timing ................................................................................................................ 12 6.3.4. Display memory write timing ................................................................................................................ 13 6.3.5. SLEEP IN command timing ................................................................................................................. 15 6.3.6. External oscillator signal timing ............................................................................................................ 16 6.3.7. LCD output timing ................................................................................................................................ 17 7. PACKAGE DIMENSIONS ......................................................................................................................................... 19 7.1. S1D13305F00A ............................................................................................................................................... 19 7.2. S1D13305F00B ............................................................................................................................................... 19 8. INSTRUCTION SET .................................................................................................................................................. 20 8.1. The Command Set ........................................................................................................................................... 20 8.2. System Control Commands ............................................................................................................................. 21 8.2.1. SYSTEM SET ...................................................................................................................................... 21 8.2.1.1. C ........................................................................................................................................... 21 8.2.1.2. M0 ......................................................................................................................................... 21 8.2.1.3. M1 ......................................................................................................................................... 21 8.2.1.4. M2 ......................................................................................................................................... 22 8.2.1.5. W/S ....................................................................................................................................... 22 8.2.1.6. IV .......................................................................................................................................... 23 8.2.1.7. FX ......................................................................................................................................... 24 8.2.1.8. WF ........................................................................................................................................ 25 8.2.1.9. FY ......................................................................................................................................... 25 8.2.1.10. C/R ....................................................................................................................................... 25 8.2.1.11. TC/R ..................................................................................................................................... 26 8.2.1.12. L/F ........................................................................................................................................ 26 8.2.1.13. AP ......................................................................................................................................... 27 8.2.2. SLEEP IN ............................................................................................................................................. 27 8.3. Display Control Commands ............................................................................................................................. 28 8.3.1. DISP ON/OFF ...................................................................................................................................... 28 8.3.1.1. D ........................................................................................................................................... 28 8.3.1.2. FC ......................................................................................................................................... 28 8.3.1.3. FP ......................................................................................................................................... 28 8.3.2. SCROLL ............................................................................................................................................... 29 8.3.2.1. C ........................................................................................................................................... 29 8.3.2.2. SL1, SL2 ............................................................................................................................... 30
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CONTENTS
8.3.3. CSRFORM ........................................................................................................................................... 34 8.3.3.1. CRX ...................................................................................................................................... 34 8.3.3.2. CRY ...................................................................................................................................... 34 8.3.3.3. CM ........................................................................................................................................ 34 8.3.4. CSRDIR ............................................................................................................................................... 34 8.3.5. OVLAY ................................................................................................................................................. 35 8.3.5.1. MX0, MX1 ............................................................................................................................. 35 8.3.5.2. DM1, DM2 ............................................................................................................................ 36 8.3.5.3. OV ........................................................................................................................................ 36 8.3.6. CGRAM ADR ....................................................................................................................................... 36 8.3.7. HDOT SCR .......................................................................................................................................... 37 8.3.7.1. D0 to D2 ............................................................................................................................... 37 8.4. Drawing Control Commands ............................................................................................................................ 37 8.4.1. CSRW .................................................................................................................................................. 37 8.4.2. CSRR ................................................................................................................................................... 38 8.5. Memory Control Commands ............................................................................................................................ 38 8.5.1. MWRITE .............................................................................................................................................. 38 8.5.2 MREAD ................................................................................................................................................ 39 9. DISPLAY CONTROL FUNCTIONS ........................................................................................................................... 40 9.1. Character Configuration ................................................................................................................................... 40 9.2. Screen Configuration ....................................................................................................................................... 42 9.2.1. Screen configuration ............................................................................................................................ 42 9.2.2. Display address scanning .................................................................................................................... 42 9.2.3. Display scan timing .............................................................................................................................. 45 9.3. Cursor Control .................................................................................................................................................. 46 9.3.1. Cursor register function ........................................................................................................................ 46 9.3.2. Cursor movement ................................................................................................................................ 46 9.3.3. Cursor display layers ........................................................................................................................... 46 9.4. Memory to Display Relationship ...................................................................................................................... 48 9.5. Scrolling ........................................................................................................................................................... 51 9.5.1. On-page scrolling ................................................................................................................................. 51 9.5.2. Inter-page scrolling .............................................................................................................................. 51 9.5.3. Horizontal scrolling ............................................................................................................................... 52 9.5.4. Bidirectional scrolling ........................................................................................................................... 53 9.5.5. Scroll units ........................................................................................................................................... 53 10. CHARACTER GENERATOR .................................................................................................................................... 54 10.1. CG Characteristics ........................................................................................................................................... 54 10.1.1. Internal character generator ................................................................................................................. 54 10.1.2. External character generator ROM ...................................................................................................... 54 10.1.3. Character generator RAM .................................................................................................................... 54 10.2. CG Memory Allocation ..................................................................................................................................... 55 10.3. Setting the Character Generator Address ........................................................................................................ 56 10.3.1. M1 = 1 .................................................................................................................................................. 56 10.3.2. CG RAM addressing example ............................................................................................................. 57 10.4. Character Codes .............................................................................................................................................. 58 11. MICROPROCESSOR INTERFACE .......................................................................................................................... 59 11.1. System Bus Interface ....................................................................................................................................... 59 11.1.1. 8080 series .......................................................................................................................................... 59 11.1.2. 6800 series .......................................................................................................................................... 59 11.2. Microprocessor Synchronization ...................................................................................................................... 59 11.2.1. Display status indication output ........................................................................................................... 59 11.2.2. Internal register access ........................................................................................................................ 59 11.2.3. Display memory access ....................................................................................................................... 59 11.3. Interface Examples .......................................................................................................................................... 61 11.3.1. Z80 to S1D13305 series interface ....................................................................................................... 61 11.3.2. 6802 to S1D13305 series interface ...................................................................................................... 61
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CONTENTS
12. DISPLAY MEMORY INTERFACE ............................................................................................................................. 62 12.1. Static RAM ....................................................................................................................................................... 62 12.2. Supply Current during Display Memory Access ............................................................................................... 63 13. OSCILLATOR CIRCUIT ............................................................................................................................................ 63 14. STATUS FLAG .......................................................................................................................................................... 63 15. RESET ....................................................................................................................................................................... 65 16. APPLICATION NOTES ............................................................................................................................................. 65 16.1. Initialization Parameters ................................................................................................................................... 65 16.1.1. SYSTEM SET instruction and parameters ........................................................................................... 65 16.1.2. Initialization example ............................................................................................................................ 66 16.1.3. Display mode setting example 1: combining text and graphics .......................................................... 72 16.1.4. Display mode setting example 2: combining graphics and graphics .................................................. 73 16.1.5. Display mode setting example 3: combining three graphics layers .................................................... 75 16.2. System Overview ............................................................................................................................................. 76 16.3 System Interconnection ................................................................................................................................... 77 16.3.1. S1D13305F .......................................................................................................................................... 77 16.4. Smooth Horizontal Scrolling ............................................................................................................................. 79 16.5. Layered Display Attributes ............................................................................................................................... 80 16.5.1. Inverse display ..................................................................................................................................... 80 16.5.2. Half-tone display .................................................................................................................................. 80 16.5.2.1. Menu pad display ................................................................................................................. 80 16.5.2.2. Graph display ....................................................................................................................... 81 16.5.3. Flashing areas ..................................................................................................................................... 81 16.5.3.1. Small area ............................................................................................................................ 81 16.5.3.2. Large area ............................................................................................................................ 81 16.6. 16 x 16-dot Graphic Display ............................................................................................................................. 81 16.6.1. Command usage .................................................................................................................................. 81 16.6.2. Kanji character display ......................................................................................................................... 81 17. INTERNAL CHARACTER GENERATOR FONT ....................................................................................................... 84 18. GLOSSARY OF TERMS ........................................................................................................................................... 85 Request for Information on S1D13305 Series ................................................................................................................. 86
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OVERVIEW/FEATURES
1. OVERVIEW
The S1D13305 series is a controller IC that can display text and graphics on LCD panel. The S1D13305 series can display layered text and graphics, scroll the display in any direction and partition the display into multiple screens. The S1D13305 series stores text, character codes and bitmapped graphics data in external frame buffer memory. Display controller functions include transferring data from the controlling microprocessor to the buffer memory, reading memory data, converting data to display pixels and generating timing signals for the buffer memory, LCD panel. The S1D13305 series has an internal character generator with 160, 5 x 7 pixel characters in internal mask ROM. The character generators support up to 64, 8 x 16 pixel characters in external character generator RAM and up to 256, 8 x 16 pixel characters in external character generator ROM.
2. FEATURES
* Text, graphics and combined text/graphics display modes * Three overlapping screens in graphics mode * Up to 640 x 256 pixel LCD panel display resolution * Programmable cursor control * Smooth horizontal and vertical scrolling of all or part of the display * 1/2-duty to 1/256-duty LCD drive * Up to 640 x 256 pixel LCD panel display resolution memory * 160, 5 x 7 pixel characters in internal mask-programmed character generator ROM * Up to 64, 8 x 16 pixel characters in external character generator RAM * Up to 256, 8 x 16 pixel characters in external character generator ROM * 6800 and 8080 family microprocessor interfaces * Low power consumption--3.5 mA operating current (VDD = 3.5V), 0.05 A standby current * Package line-up S1D13305F00A S1D13305F00B Package QFP5-60 pin QFP6-60 pin
* 2.7 to 5.5 V (S1D13305F)
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BLOCK DIAGRAM
3. BLOCK DIAGRAM
Video RAM Character Generator RAM
VA0 to VA15
Character Generator ROM
YSCL, YD, YDIS VD0 to VD7
LCD
VRD, VWR (S1D13305F)
Video RAM Interface
Input/Output Register
LCD Controller
Cursor Address Controller
Display Address Controller
Refresh Counter
Dot Counter
Character Generator ROM
Layered Controller
Microprocessor Interface
Oscillator
A0, CS
D0 to D7
RD, WR
SEL0 SEL1
RES
XG
XD0 to XD3
LP, WF
VCE
XSCL
XD
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PINOUTS
4. PINOUTS
S1D13305F00A
XG SEL1 SEL2 WR RD NC NC RES VRD VCE VWR VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7
S1D13305F00B
VD4 VD5 VD6 VD7 YSCL YD YDIS WF LP VSS XSCL XECL XD0 XD1 XD2
45 46 31 30
XD CS A0 VDD D0 D1 D2 D3 D4 D5 D6
50
45
40
60 1 5
S1D13305F00A
Index
30 29
VA8 VA9 VA10 VA11 VA12 VA13 NC VA14 VA15 VD0 VD1 VD2
6
10
15
20
VD3 VD2 VD1 VD0 VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 NC
S1D13305F00B
Index
60 1
16 15
XD3 D7 D6 D5 D4 D3 D2 D1 D0 VDD A0 CS XD XG SEL1
D7 XD3 XD2 XD1 XD0 XECL XSCL VSS LP WF YDIS YD YSCL VD7 VD6 VD5 VD4 VD3
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VA5 VA4 VA3 VA2 VA1 VA0 VWR VCE VRD RES NC NC RD WR SEL 2
3
PIN DESCRIPTION
5.
PIN DESCRIPTION
5.1. S1D13305F00A/00B Pin Summary
Name VA0 to VA15 VWR VCE VRD RES NC RD WR SEL2 SEL1 XG XD CS A0 VDD D0 to D7 XD0 to XD3 XECL XSCL VSS LP WF YDIS YD YSCL VD0 to VD7 Number S1D13305F00A 27 to 28 30 to 43 44 45 46 47 28, 48, 49 50 51 52 53 54 55 56 57 58 59 to 60 1 to 6 7 to 10 11 12 13 14 15 16 17 18 19 to 26 S1D13305F00B 1 to 6 50 to 59 7 8 9 10 11, 12, 60 13 14 15 16 17 18 19 20 21 22 to 29 30 to 33 34 35 36 37 38 39 40 41 42 to 49 Type Output Output Output Output Input -- Input Input Input Input Input Output Input Input Supply Input/output Output Output Output Supply Output Output Output Output Output Input/output Description VRAM address bus VRAM write signal Memory control signal VRAM read signal Reset No connection 8080 family: Read signal 6800 family: Enable clock (E) 8080 family: Write signal 6800 family: R/W signal 8080 or 6800 family interface select 8080 or 6800 family interface select Oscillator connection Oscillator connection Chip select Data type select 2.7 to 5.5V supply Data bus X-driver data X-driver enable chain clock X-driver data shift clock Ground Latch pulse Frame signal Power-down signal when display is blanked Scan start pulse Y-driver shift clock VRAM data bus
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PIN DESCRIPTION
5.2. Pin Functions
5.2.1. Power supply
Pin Name VDD VSS Function 2.7 to 5.5V supply. This may be the same supply as the controlling microprocessor. Ground
Note: The peak supply current drawn by the S1D13305 series may be up to ten times the average supply current. The power supply impedance must be kept as low as possible by ensuring that supply lines are sufficiently wide and by placing 0.47 F decoupling capacitors that have good high-frequency response near the device's supply pins.
5.2.2. Oscillator
Pin Name XG XD Function Crystal connection for internal oscillator (See section 13). This pin can be driven by an external clock source that satisfies the timing specifications of the EXT 0 signal (See section 6.3.6). Crystal connection for internal oscillator. Leave this pin open when using an external clock source.
5.2.3. Microprocessor interface
Pin Name D0 to D7 Function Tristate input/output pins. Connect these pins to an 8- or 16-bit microprocessor bus. Microprocessor interface select pin. The S1D13305 series supports both 8080 family processors (such as the 8085 and Z80(R)) and 6800 family processors (such as the 6802 and 6809).
SEL1 0 1 SEL2* 0 0 Interface 8080 family 6800 family A0 A0 A0 RD RD E WR WR R/W CS CS CS
SEL1, SEL2
Note: SEL1 should be tied directly to VDD or VSS to prevent noise. If noise does appear on SEL1, decouple it to ground using a capacitor placed as close to the pin as possible.
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PIN DESCRIPTION
Pin Name 8080 family interface
A0 0 1 0 1 RD 0 0 1 1 WR 1 1 0 0
Function
Function Status flag read Display data and cursor address read Display data and parameter write Command write
A0
6800 family interface
A0 0 1 0 1 R/W 1 1 0 0 E 1 1 1 1 Function Status flag read Display data and cursor address read Display data and parameter write Command write
RD or E
When the 8080 family interface is selected, this signal acts as the active-LOW read strobe. The S1D13305 series output buffers are enabled when this signal is active. When the 6800 family interface is selected, this signal acts as the active-HIGH enable clock. Data is read from or written to the S1D13305 series when this clock goes HIGH. When the 8080 family interface is selected, this signal acts as the active-LOW write strobe. The bus data is latched on the rising edge of this signal.
WR or R/W
When the 6800 family interface is selected, this signal acts as the read/write control signal. Data is read from the S1D13305 series if this signal is HIGH, and written to the S1D13305 series if it is LOW. Chip select. This active-LOW input enables the S1D13305 series. It is usually connected to the output of an address decoder device that maps the S1D13305 series into the memory space of the controlling microprocessor. This active-LOW input performs a hardware reset on the S1D13305 series. It is a Schmitt-trigger input for enhanced noise immunity; however, care should be taken to ensure that it is not triggered if the supply voltage is lowered.
CS
RES
5.2.4. Display memory control
The S1D13305 series can directly access static RAM and PROM. The designer may use a mixture of these two
Pin Name
types of memory to achieve an optimum trade-off between low cost and low power consumption.
Function
16-bit display memory address. When accessing character generator RAM or ROM, VA0 to VA0 to VA15 VA3, reflect the lower 4 bits of the S1D13305 series's row counter. VD0 to VD7 8-bit tristate display memory data bus. These pins are enabled when VR/W is LOW. VWR Active-LOW display memory write control output.
VRD Active-LOW display memory read control output.
VCE
Active-LOW static memory standby control signal. VCE can be used with CS.
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PIN DESCRIPTION/SPECIFICATIONS
5.2.5. LCD drive signals
In order to provide effective low-power drive for LCD matrixes, the S1D13305 series can directly control both the X- and Y-drivers using an enable chain.
Pin Name XD0 to XD3 XSCL XECL LP Function 4-bit X-driver (column drive) data outputs. Connect these outputs to the inputs of the X-driver chips. The falling edge of XSCL latches the data on XD0 to XD3 into the input shift registers of the X-drivers. To conserve power, this clock halts between LP and the start of the following display line (See section 6.3.7). The falling edge of XECL triggers the enable chain cascade for the X-drivers. Every 16th clock pulse is output to the next X-driver. LP latches the signal in the X-driver shift registers into the output data latches. LP is a fallingedge triggered signal, and pulses once every display line. Connect LP to the Y-driver shift clock on modules. LCD panel AC drive output. The WF period is selected to be one of two values with SYSTEM SET command. The falling edge of YSCL latches the data on YD into the input shift registers of the Y-drivers. YSCL is not used with driver ICs which use LP as the Y-driver shift clock. YD is the data pulse output for the Y drivers. It is active during the last line of each frame, and is shifted through the Y drivers one by one (by YSCL), to scan the display's common connections. Power-down output signal. YDIS is HIGH while the display drive outputs are active. YDIS goes LOW one or two frames after the sleep command is written to the S1D13305 series. All Y-driver outputs are forced to an intermediate level (de-selecting the display segments) to blank the display. In order to implement power-down operation in the LCD unit, the LCD power drive supplies must also be disabled when the display is disabled by YDIS.
WF YSCL YD
YDIS
6. SPECIFICATIONS
6.1. Absolute Maximum Ratings
Parameter Supply voltage range Input voltage range Power dissipation Operating temperature range Storage temperature range Soldering temperature (10 seconds). See note 1.
Notes: 1. The humidity resistance of the flat package may be reduced if the package is immersed in solder. Use a soldering technique that does not heatstress the package. 2. If the power supply has a high impedance, a large voltage differential can occur between the input and supply voltages. Take appropriate care with the power supply and the layout of the supply lines. (See section 6.2.) 3. All supply voltages are referenced to VSS = 0V.
Symbol VDD VIN PD Topg Tstg Tsolder
Rating -0.3 to 7.0 -0.3 to VDD + 0.3 300 -20 to 75 -65 to 150 260
Unit V V mW C C C
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SPECIFICATIONS
6.2. S1D13305
VDD = 4.5 to 5.5V, VSS = 0V, Ta = -20 to 75C Parameter Supply voltage Register data retention voltage Input leakage current Output leakage current Operating supply current Quiescent supply current Oscillator frequency External clock frequency Oscillator feedback resistance TTL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage CMOS HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Open-drain LOW-level output voltage Schmitt-trigger Rising-edge threshold voltage Falling-edge threshold voltage
Notes: 1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VRD, VWR and VCE are TTL-level inputs. 2. SEL1 is CMOS-level inputs. YD, XD0 to XD3, XSCL, LP, WF, YDIS are CMOS-level outputs. 3. RES is a Schmitt-trigger input. The pulsewidth on RES must be at least 200 s. Note that pulses of more than a few seconds will cause DC voltages to be applied to the LCD panel. 4. fOSC = 10 MHz, no load (no display memory), internal character generator, 256 x 200 pixel display. The operating supply current can be reduced by approximately 1 mA by setting both CLO and the display OFF. 5. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become high-impedance, the input state immediately prior to that is held. Because of the feedback circuit, input current flow occurs when the inputs are in an intermediate state. 6. Because the oscillator circuit input bias current is in the order of A, design the printed circuit board so as to reduce leakage currents.
Symbol VDD VOH ILI ILO Iopr IQ fOSC fCL Rf VIHT VILT VOHT VOLT VIHC VILC VOHC VOLC VOLN VT+ VT-
Condition
Rating Min. 4.5 2.0 -- -- -- -- 1.0 1.0 0.5 0.5VDD VSS 2.4 -- Typ. 5.0 -- 0.05 0.10 11 0.05 -- -- 1.0 -- -- -- -- -- -- -- -- -- 0.7VDD 0.3VDD Max. 5.5 6.0 2.0 5.0 15 20.0 10.0 10.0 3.0 VDD 0.2VDD -- VSS + 0.4 VDD 0.2VDD -- VSS + 0.4 VSS + 0.4 0.8VDD 0.5VDD
Unit V V A A mA A MHz MHz M V V V V V V V V V V V
VI = VDD. See note 5. VI = VSS. See note 5. See note 4. Sleep mode, VOSC1 = VCS = VRD = VDD Measured at crystal, 47.5% duty cycle. See note 6. See note 1. See note 1. IOH = -5.0 mA. See note 1. IOL = 5.0 mA. See note 1.
See note 2. 0.8VDD See note 2. VSS IOH = -2.0 mA. See note 2.VDD - 0.4
IOH = 1.6 mA. See note 2.
-- -- 0.5VDD 0.2VDD
IOL = 6.0 mA. See note 3. See note 3.
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SPECIFICATIONS
VDD = 2.7 to 4.5 V, VSS = 0 V, Ta = -20 to 75C unless otherwise noted
Rating Parameter Supply voltage Register data retention voltage Input leakage current Output leakage current Operating supply current Symbol VDD VOH ILI ILO Iopr VI = VDD. See note 5. VI = VSS. See note 5. VDD = 3.5 V. See note 4. See note 4. Quiescent supply current Oscillator frequency External clock frequency Oscillator feedback resistance TTL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage CMOS HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Open-drain LOW-level output voltage Schmitt-trigger Rising-edge threshold voltage Falling-edge threshold voltage VT+ VT- See note 3. See note 3. 0.5 VDD 0.2 VDD 0.7 VDD 0.3 VDD 0.8 VDD 0.5 VDD V V VOLN IOL = 6.0 mA. -- -- VSS + 0.4 V VIHC VILC VOHC VOLC See note 2. See note 2. IOH = -2.0 mA. See note 2. IOH = 1.6 mA. See note 2. 0.8 VDD VSS VDD - 0.4 -- -- -- -- -- VDD 0.2 VDD -- VSS + 0.4 V V V V VIHT VILT VOHT VOLT See note 1. See note 1. IOH = -3.0 mA. See note 1. IOL = 3.0 mA. See note 1. 0.5 VDD VSS 2.4 -- -- -- -- -- VDD 0.2 VDD -- VSS + 0.4 V V V V IQ fOSC fCL Rf Sleep mode, VOSC1 = VCS = VRD = VDD Measured at crystal, 47.5% duty cycle. See note 6. Condition Min. 2.7 2.0 -- -- -- -- -- 1.0 1.0 0.7 Typ. 3.5 -- 0.05 0.10 3.5 -- 0.05 -- -- -- Max. 4.5 6.0 2.0 5.0 -- 7.0 20.0 8.0 8.0 3.0 A MHz MHz M V V A A mA Unit
Notes
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VRD, VWR and VCE are TTL-level inputs. 2. SEL1 is CMOS-level inputs. YD, XD0 to XD3, XSCL, LP, WF, YDIS are CMOS-level outputs. 3. RES is a Schmitt-trigger input. The pulsewidth on RES must be at least 200 s. Note that pulses of more than a few seconds will cause DC voltages to be applied to the LCD panel. 4.
fOSC = 10 MHz, no load (no display memory), internal character generator, 256 x 200 pixel display.
be reduced by approximately 1 mA by setting both CLO and the display OFF.
The operating supply current can
5. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become high-impedance, the input state immediately prior to that is held. Because of the feedback circuit, input current flow occurs when the inputs are in an intermediate state. 6. Because the oscillator circuit input bias current is in the order of A, design the printed circuit board so as to reduce leakage currents.
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SPECIFICATIONS
6.3. S1D13305F Timing Diagrams
6.3.1. 8080 family interface timing
AO, CS tAW8 tCYC8 WR, RD tCC tDS8 D0 to D7 (Write) tACC8 D0 to D7 (Read) tOH8 tDH8 tAH8
Ta = -20 to 75C Signal A0, CS WR, RD Symbol tAH8 tAW8 tCYC8 tCC tDS8 D0 to D7 tDH8 tACC8 tOH8 Parameter Address hold time Address setup time System cycle time Strobe pulsewidth Data setup time Data hold time RD access time Output disable time VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V Min. Max. Min. Max. 10 0
See note.
Unit ns ns ns ns ns ns ns ns
Condition
120 120 5 -- 10
-- -- -- -- -- -- 50 50
10 0
See note.
150 120 5 -- 10
-- -- -- -- -- -- 80 55
CL = 100pF
Note: For memory control and system control commands: tCYC8 = 2tC + tCC + tCEA + 75 > tACV + 245 For all other commands: tCYC8 = 4tC + tCC + 30
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SPECIFICATIONS
6.3.2. 6800 family interface timing
E tCYC6 tAW6 R/W tAH6 A0, CS tDH6 tDS6 D0 to D7 (Write) tACC6 D0 to D7 (Read) tOH6 tEW
Note: tCYC6 indicates the interval during which CS is LOW and E is HIGH.
Ta = -20 to 75C Signal A0, CS, R/W Symbol tCYC6 tAW6 tAH6 tDS6 tDH6 tOH6 tACC6 tEW Parameter System cycle time Address setup time Address hold time Data setup time Data hold time Output disable time Access time Enable pulsewidth VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V Min. Max. Min. Max. See note. -- See note. -- 0 -- 10 -- 0 -- 0 -- 100 0 10 -- 120 -- -- 50 85 -- 120 0 10 -- 150 -- -- 75 130 -- Unit ns ns ns ns ns ns ns ns CL = 100 pF Condition
D0 to D7
E
Note: For memory control and system control commands: tCYC6 = 2tC + tEW + tCEA + 75 > tACV + 245 For all other commands: tCYC6 = 4tC + tEW + 30
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SPECIFICATIONS
6.3.3. Display memory read timing
EXT0 tC tW VCE tCE tW
tCYR VA0 to VA15 tASC tAHC tRCH VR/W tRCS tACV VD0 to VD7 tCEA tCE3 tOH2
Ta = -20 to 75C Signal EXT 0 VCE tCE tCYR VA0 to VA15 tASC tAHC tRCS VRD tRCH tACV tCEA tOH2 tCE3 Symbol tC tW Parameter Clock period VCE HIGH-level pulsewidth VCE LOW-level pulsewidth VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V Min. Max. Min. Max. 100 tC - 50 2tC - 30 -- -- -- 125 tC - 50 2tC - 30 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns CL = 100 pF Condition
VD0 to VD7
Read cycle time 3tC -- 3tC -- Address setup time to -- tC - 100 -- tC - 70 falling edge of VCE Address hold time from -- 2tC - 40 -- 2tC - 30 falling edge of VCE Read cycle setup time to tC - 45 -- tC - 60 -- falling edge of VCE Read cycle hold time -- 0.5tC -- 0.5tC from rising edge of VCE Address access time -- 3tC - 100 -- 3tC - 115 VCE access time -- 2tC - 80 -- 2tC - 90 Output data hold time 0 -- 0 -- VCE to data off time 0 -- 0 --
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SPECIFICATIONS
6.3.4. Display memory write timing
tC
EXT O
tW
VCE
tCE
tASC tAHC
VA0 to VA15
tCA
tAS tWSC
tWHC
tAH2
VR/W
tDSC
VD0 to VD7
tDH2 tDHC
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SPECIFICATIONS
Ta = -20 to 75C Signal EXT 0 VCE tCE tCYW tAHC tASC VA0 to VA15 tCA tAS tAH2 tWSC VWR tWHC tDSC VD0 to VD7 tDHC tDH2 Symbol tC tW Parameter Clock period VCE HIGH-level pulsewidth VCE LOW-level pulsewidth Write cycle time Address hold time from falling edge of VCE Address setup time to falling edge of VCE Address hold time from rising edge of VCE Address setup time to falling edge of VWR Address hold time from rising edge of VWR Write setup time to falling edge of VCE Write hold time from falling edge of VCE VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V Min. Max. Min. Max. 100 -- 125 -- tC - 50 2tC - 30 3tC 2tC - 30 tC - 70 0 0 10 tC - 80 2tC - 20 -- -- -- -- -- -- -- -- -- -- -- -- 50 tC - 50 2tC - 30 3tC 2tC - 40 tC - 110 0 0 10 tC - 115 2tC - 20 tC - 125 2tC - 30 5 -- -- -- -- -- -- -- -- -- -- -- -- 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns CL = 100 pF Condition
Data input setup time to tC - 85 falling edge of VCE Data input hold time 2tC - 30 from falling edge of VCE Data hold time from 5 rising edge of VWR
Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read from the memory is placed on the bus.
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SPECIFICATIONS
6.3.5. SLEEP IN command timing
VCE
SLEEP IN write SYSTEM SET write
tWRL
tWRD
WR (Command input)
YDIS
Ta = -20 to 75C Signal Symbol tWRD WR tWRL
Notes: 1. tWRD = 18tC + tOSS + 40 (tOSS is the time delay from the sleep state until stable operation) 2. tWRL = 36tC x [TC/R] x [L/F] + 70
Parameter VCE falling-edge delay time YDIS falling-edge delay time
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V Min. Max. Min. Max.
See note 1.
Unit ns ns
Condition
--
See note 2.
See note 1.
--
See note 2.
--
--
CL = 100 pF
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SPECIFICATIONS
6.3.6. External oscillator signal timing
tRCL EXT0 tWL tC tWH tFCL
Ta = -20 to 75C Signal Symbol tRCL tFCL EXT 0 tWH tWL tC
Notes: 1. 2. (tC - tRCL - tFCL) x (tC - tRCL - tFCL) x 475 < tWH, tWL 1000 525 > tWH, tWL 1000
Parameter External clock rise time External clock fall time External clock HIGH-level pulsewidth External clock LOW-level pulsewidth External clock period
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V Min. Max. Min. Max -- -- 15 15 -- -- 15 15
Unit ns ns ns ns ns
Condition
See note 1. See note 2. See note 1. See note 2. See note 1. See note 2. See note 1. See note 2.
100
--
125
--
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6.3.7. LCD output timing
The following characteristics are for a 1/64 duty cycle.
Row
62
63
64
1
2
3
4
60
61
62
63
64
LP 1 frame time YD
WF
WF 1 line time
Row 64 LP
Row 1
Row 2
XSCL
XD0 to XD3 (14) (15)
(16)
(1)
(15) (16)(1) (2) (3)
(15) (16)
(1)
tr XSCL
tWX
tf
tCX
tDS tLS XD0 to XD3 tWL tLD LP
tDH
tDHY tDF WF(B)
YD
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SPECIFICATIONS
Ta = -20 to 75C Signal Symbol tr tf tCX tWX tDH tDS tLS tWL tLD tDF tDHY Parameter Rise time Fall time Shift clock cycle time XSCL clock pulsewidth X data hold time VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V Min. Max. Min. Max -- -- 4tC 2tC - 60 2tC - 50 30 30 -- -- -- -- -- -- -- 50 -- -- -- 4tC 2tC - 60 2tC - 50 2tC - 105 2tC - 50 4tC - 120 0 -- 2tC - 20 40 40 -- -- -- -- -- -- -- 50 -- Unit ns ns ns ns ns ns ns ns ns ns ns Condition
XSCL XD0 to XD3 LP WF YD
X data setup time 2tC - 100 Latch data setup time 2tC - 50 LP pulsewidth 4tC - 80 LP delay time from XSCL 0 Permitted WF delay -- Y data hold time 2tC - 20
CL = 100 pF
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PACKAGE DIMENSIONS
7. PACKAGE DIMENSIONS
Unit: mm
7.1. S1D13305F00A
QFP5-60 pin
7.2. S1D13305F00B
QFP6-60 pin
25.6 0.4 20.0 0.1 54 36
17.6 0.4 14.0 0.2 45 46 31 30
55
35
14.0 0.2
16 15 0.35 0.15
14.0 0.1
60 1 5
30 Index 29
19.6 0.4
Index
24
60 1
6
0.15 0.05
2.7 0.1
0.15 0.05
2.7 0.1
1.0 0.1
0.35 0.1
23
0.8 0.15
0 to 12
17.6 0.4
0 to 12
1.5 0.3
2.8
0.8 0.3
1.8
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8. INSTRUCTION SET
8.1. The Command Set
Table 1. Command set
Code Class Command RD WR A0 D7 D6 D5 D4 D3 D2 D1 D0 System control SYSTEM SET SLEEP IN DISP ON/OFF SCROLL CSRFORM Display control CGRAM ADR CSRDIR HDOT SCR OVLAY Drawing control Memory control CSRW CSRR MWRITE MREAD 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 0 1 D 0 1 0 40 Initialize device and display Hex Command Description Command Read Parameters No. of Bytes 8 0 1 10 2 2 0 1 1 2 2 -- -- Section 8.2.1 8.2.2 8.3.1 8.3.2 8.3.3 8.3.6 8.3.4 8.3.7 8.3.5 8.4.1 8.4.2 8.5.1 8.5.2
53 Enter standby mode 58, Enable and disable dis59 play and display flashing 44 Set display start address and display regions
5D Set cursor type Set start address of char5C acter generator RAM
4C CD CD Set direction of cursor to 10 movement 4F 1 1 1 1 1 1 0 1 0 1 0 1 5A 5B Set horizontal scroll position
Set display overlay format 46 Set cursor address 42 Write to display memory Read from display 43 memory
47 Read cursor address
Notes: 1. In general, the internal registers of the S1D13305 series are modified as each command parameter is input. However, the microprocessor does not have to set all the parameters of a command and may send a new command before all parameters have been input. The internal registers for the parameters that have been input will have been changed but the remaining parameter registers are unchanged. 2-byte parameters (where two bytes are treated as 1 data item) are handled as follows: a. CSRW, CSRR: Each byte is processed individually. The microprocessor may read or write just the low byte of the cursor address. b. SYSTEM SET, SCROLL, CGRAM ADR: Both parameter bytes are processed together. If the command is changed after half of the parameter has been input, the single byte is ignored. 2. APL and APH are 2-byte parameters, but are treated as two 1-byte parameters.
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8.2. System Control Commands
8.2.1. SYSTEM SET
Initializes the device, sets the window sizes, and selects the LCD interface format. Since this command sets the basic operating parameters of the S1D13305 series, an
MSB D7 C 0 D6 1 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
incorrect SYSTEM SET command may cause other commands to operate incorrectly.
LSB A0 1 WR 0 RD 1
P1
0
0
IV
1
W/S
M2
M1
M0
0
0
1
P2
WF
0
0
0
0
FX
0
0
1
P3
0
0
0
0
FY
0
0
1
P4
C/R
0
0
1
P5
TC/R
0
0
1
P6
L/F
0
0
1
P7
APL
0
0
1
P8
APH
0
0
1
Figure 1. SYSTEM SET instruction
8.2.1.1. C This control byte performs the following: 1. Resets the internal timing generator 2. Disables the display 3. Cancels sleep mode Parameters following P1 are not needed if only canceling sleep mode. 8.2.1.2. M0 Selects the internal or external character generator ROM. The internal character generator ROM contains 160, 5 x 7 pixel characters, as shown in figure 70. These characters are fixed at fabrication by the metallization mask. The external character generator ROM, on the other hand, can contain up to 256 user-defined characters. M0 = 0: Internal CG ROM M0 = 1: External CG ROM
Note that if the CG ROM address space overlaps the display memory address space, that portion of the display memory cannot be written to. 8.2.1.3. M1 Selects the memory configuration for user-definable characters. The CG RAM codes select one of the 64 codes shown in figure 46. M1 = 0: No D6 correction. The CG RAM1 and CG RAM2 address spaces are not contiguous, the CG RAM1 address space is treated as character generator RAM, and the CG RAM2 address space is treated as character generator ROM. M1 = 1: D6 correction. The CG RAM1 and CG RAM2 address spaces are contiguout and are both treated as character generator RAM.
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8.2.1.4. M2 Selects the height of the character bitmaps. Characters more than 16 pixels high can be displayed by creating a bitmap for each portion of each character and using the S1D13305 series graphics mode to reposition them. M2 = 0: 8-pixel character height (2716 or equivalent ROM) M2 = 1: 16-pixel character height (2732 or equivalent ROM)
8.2.1.5. W/S Selects the LCD drive method. W/S = 0: Single-panel drive W/S = 1: Dual-panel drive
EI
X driver
X driver
YD
Y driver
LCD
Figure 2. Single-panel display
EI
X driver
X driver
YD
Upper Panel Y driver Lower Panel
X driver
X driver
Figure 3. Above and below two-panel display
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EI YD
X driver
X driver
X driver
X driver
Y driver
Left Panel
Right Panel
Figure 4. Left-and-right two-panel display Note There are no Seiko Epson LCD units in the configuration shown in Figure 4. Table 2. LCD parameters
Parameter C/R TC/R L/F SL1 SL2 SAD1 SAD2 SAD3 SAD4 Cursor movement range
Notes: 1. See table 26 for further details on setting the C/R and TC/R parameters when using the HDOT SCR command. 2. The value of SL when IV = 0 is equal to the value of SL when IV = 1, plus one.
W/S = 0 IV = 1 C/R TC/R L/F 00H to L/F 00H to L/F IV = 0 C/R TC/R (See note 1.) L/F 00H to L/F + 1 (See note 2.) IV = 1 C/R TC/R L/F (L/F) / 2
W/S = 1 IV = 0 C/R TC/R L/F (L/F) / 2
00H to L/F + 1 (L/F) / 2 (L/F) / 2 (See note 2.) First screen block First screen block First screen block First screen block Second screen block Second screen block Second screen block Second screen block Third screen block Invalid Third screen block Invalid Third screen block Third screen block Fourth screen block Fourth screen block Above-and-below configuration: continuous movement over whole screen
Continuous movement over whole screen
8.2.1.6. IV Screen origin compensation for inverse display. IV is usually set to 1. The best way of displaying inverted characters is to Exclusive-OR the text layer with the graphics background layer. However, inverted characters at the top or left of the screen are difficult to read as the character origin is at the top-left of its bitmap and there are no background pixels either above or to the left of these characters.
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INSTRUCTION SET
The IV flag causes the S1D13305 series to offset the text screen against the graphics back layer by one vertical pixel. Use the horizontal pixel scroll function (HDOT SCR) to shift the text screen 1 to 7 pixels to the right. All characters will then have the necessary surrounding background pixels that ensure easy reading of the inverted characters. See Section 10.5 for information on scrolling. IV = 0: Screen top-line correction IV = 1: No screen top-line correction
Display start point Back layer HDOT SCR Character IV 1 dot
8.2.1.7. FX Define the horizontal character size. The character width in pixels is equal to FX + 1, where FX can range from 00 to 07H inclusive. If data bit 3 is set (FX is in the range 08 to 0FH) and an 8-pixel font is used, a space is inserted between characters. Table 3. Horizontal character size selection
FX HEX 00 01 07 D3 D2 D1 D0 0 0 0 0 0 1 0 0 1 0 1 1 [FX] character width (pixels) 1 2 8
Dots 1 to 7
Figure 5. IV and HDOT SCR adjustment
Since the S1D13305 series handles display data in 8-bit units, characters larger than 8 pixels wide must be formed from 8-pixel segments. As Figure 6 shows, the remainder of the second eight bits are not displayed. This also applies to the second screen layer. In graphics mode, the normal character field is also eight pixels. If a wider character field is used, any remainder in the second eight bits is not displayed.
FX
FX
FY 8 bits FY 8 bits 8 bits 8 bits
Address A
Address B
Non-display area
Figure 6. FX and FY display addresses
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8.2.1.8. WF Selects the AC frame drive waveform period. WF is usually set to 1. WF = 0: 16-line AC drive WF = 1: two-frame AC drive In two-frame AC drive, the WF period is twice the frame period. In 16-line AC drive, WF inverts every 16 lines. Although 16-line AC drive gives a more readable display, horizontal lines may appear when using high LCD drive voltages or at high viewing angles. 8.2.1.9. FY Sets the vertical character size. The height in pixels is equal to FY + 1. FY can range from 00 to 0FH inclusive. Set FY to zero (vertical size equals one) when in graphics mode. Table 4. Vertical character size selection
HEX 00 01 07 0E 0F D3 0 0 0 1 1 FY D2 D1 D0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 [FY] character height (pixels) 1 2 8 15 16
8.2.1.10. C/R Sets the address range covered by one display line, that is, the number of characters less one, multiplied by the number of horizontal bytes per character. C/R can range from 0 to 239. For example, if the character width is 10 pixels, then the address range is equal to twice the number of characters, less 2. See Section 16.1.1 for the calculation of C/R. [C/R] cannot be set to a value greater than the address range. It can, however, be set smaller than the address range, in which case the excess display area is blank. The number of excess pixels must not exceed 64.
Table 5. Display line address range
HEX 00 01 4F EE EF D7 0 0 0 1 1 D6 0 0 1 1 1 D5 0 0 0 1 1 C/R D4 0 0 0 0 0 D3 0 0 1 1 1 D2 0 0 1 1 1 D1 0 0 1 1 1 D0 0 1 1 0 1 [C/R] bytes per display line 1 2 80 239 240
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8.2.1.11. TC/R Sets the length, including horizontal blanking, of one line. The line length is equal to TC/R + 1, where TC/ R can range from 0 to 255. TC/R must be greater than or equal to C/R + 4. Provided this condition is satisfied, [TC/R] can be set according to Table 6. Line length selection
HEX 00 01 52 FE FF D7 0 0 0 1 1 D6 0 0 1 1 1 D5 0 0 0 1 1 TC/R D4 0 0 1 1 1 D3 0 0 0 1 1 D2 0 0 0 1 1
the equation given in section 16.1.1 in order to hold the frame period constant and minimize jitter for any given main oscillator frequency, fOSC.
D1 0 0 1 1 1
D0 0 1 0 0 1
[TC/R] line length (bytes) 1 2 83 255 256
8.2.1.12. L/F Sets the height, in lines, of a frame. The height in lines is equal to L/F + 1, where L/F can range from 0 to 255. Table 7. Frame height selection
HEX 00 01 7F FE FF D7 0 0 0 1 1 D6 0 0 1 1 1 D5 0 0 1 1 1 L/F D4 0 0 1 1 1 D3 0 0 1 1 1 D2 0 0 1 1 1 D1 0 0 1 1 1 D0 0 1 1 0 1 [L/F] lines per frame 1 2 128 255 256
If W/S is set to 1, selecting two-screen display, the number of lines must be even and L/F must, therefore, be an odd number.
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8.2.1.13. AP Defines the horizontal address range of the virtual screen. APL is the least significant byte of the address.
APL APH AP7 AP15 AP6 AP14 AP5 AP13 AP4 AP12 AP3 AP11 AP2 AP10 AP1 AP9 AP0 AP8
Figure 7. AP parameters Table 8. Horizontal address range
Hex code APH 0 0 0 F F 0 0 0 F F 0 0 5 F F APL 0 1 0 E F [AP] addresses per line 0 1 80 216 - 2 216 - 1
Blank data is sent to the X-drivers, and the Y-drivers have their bias supplies turned off by the YDIS signal. Using the YDIS signal to disable the Y-drivers guards against any spurious displays. The internal registers of the S1D13305 series maintain their values during the sleep state. The display memory control pins maintain their logic levels to ensure that the display memory is not corrupted. The S1D13305 series can be removed from the sleep state by sending the SYSTEM SET command with only the P1 parameter. The DISP ON command should be sent next to enable the display.
MSB C 0 1 0 1 0 0 1 LSB 1
Figure 9. SLEEP IN instruction
Display area
C/R
Display memory limit
AP
Figure 8. AP and C/R relationship
8.2.2. SLEEP IN
Places the system in standby mode. This command has no parameter bytes. At least one blank frame after receiving this command, the S1D13305F halts all internal operations, including the oscillator, and enters the sleep state.
1. The YDIS signal goes LOW between one and two frames after the SLEEP IN command is received. Since YDIS forces all display driver outputs to go to the deselected output voltage, YDIS can be used as a power-down signal for the LCD unit. This can be done by having YDIS turn off the relatively highpower LCD drive supplies at the same time as it blanks the display. 2. Since all internal clocks in the S1D13305 series are halted while in the sleep state, a DC voltage will be applied to the LCD panel if the LCD drive supplies remain on. If reliability is a prime consideration, turn off the LCD drive supplies before issuing the SLEEP IN command. 3. Note that, although the bus lines become high impedance in the sleep state, pull-up or pull-down resistors on the bus will force these lines to a known state.
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8.3. Display Control Commands
8.3.1. DISP ON/OFF
Turns the whole display on or off. The single-byte parameter enables and disables the cursor and layered screens, and sets the cursor and screen flash rates. The cursor can be set to flash over one character or over a whole line.
MSB C 0 1 0 1 1 0 0 LSB D
8.3.1.3. FP Each pair of bits in FP sets the attributes of one screen block, as follows. The display attributes are as follows: Table 10. Screen block attribute selection
FP1 FP3 FP0 FP2 FP4 0 1 0 1 ON First screen block (SAD1) Second screen block (SAD2, SAD4). See note. Third screen block (SAD3) OFF (blank) No flashing Flash at fFR/32 Hz (approx. 2 Hz) Flash at fFR/4 Hz (approx. 16 Hz)
P1 FP5 FP4 FP3 FP2 FP1 FP0 FC1 FC0
FP5 0 0 1 1
Figure 10. DISP ON/OFF parameters 8.3.1.1. D Turns the display ON or OFF. The D bit takes precedence over the FP bits in the parameter. D = 0: Display OFF D = 1: Display ON 8.3.1.2. FC Enables/disables the cursor and sets the flash rate. The cursor flashes with a 70% duty cycle (ON/OFF). Table 9. Cursor flash rate selection
FC1 0 0 1 1 FC0 0 1 0 1 ON Cursor display OFF (blank) No flashing Flash at fFR/32 Hz (approx. 2 Hz) Flash at fFR/64 Hz (approx. 1 Hz)
Note If SAD4 is enabled by setting W/S to 1, FP3 and FP2 control both SAD2 and SAD4. The attributes of SAD2 and SAD4 cannot be set independently.
Note: As the MWRITE command always enables the cursor, the cursor position can be checked even when performing consecutive writes to display memory while the cursor is flashing.
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8.3.2. SCROLL
8.3.2.1. C Sets the scroll start address and the number of lines per scroll block. Parameters P1 to P10 can be omitted if not
MSB C P1 P2 P3 P4 P5 P6 P7 P8 P9 0 A7 1 A6 0 A5 0 A4 0 A3 1 A2 0 A1 A9 L1 A1 A9 L1 A1 A9 A1 A9
required. The parameters must be entered sequentially as shown in Figure 11.
LSB 0 A0 (SAD 1L) A8 (SAD 1H) L0 (SL 1) A0 (SAD 2 L) A8 (SAD 2H) L0 (SL 2) A0 (SAD 3L) A8 (SAD 3H) A0 (SAD 4L) A8 (SAD 4H)
A15 A14 A13 A12 A11 A10 L7 A7 L6 A6 L5 A5 L4 A4 L3 A3 L2 A2
A15 A14 A13 A12 A11 A10 L7 A7 L6 A6 L5 A5 L4 A4 L3 A3 L2 A2
A15 A14 A13 A12 A11 A10 A7 A6 A5 A4 A3 A2
P10 A15 A14 A13 A12 A11 A10
Figure 11. SCROLL instruction parameters
Note: Set parameters P9 and P10 only if both two-screen drive (W/S = 1) and two-layer configuration are selected. SAD4 is the fourth screen block display start address.
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Table 11. Screen block start address selection
SL1, SL2 HEX 00 01 7F FE FF L7 0 0 0 1 1 L6 0 0 1 1 1 L5 0 0 1 1 1 L4 0 0 1 1 1 L3 0 0 1 1 1 L2 0 0 1 1 1 L1 0 0 1 1 1 L0 0 1 1 0 1 [SL] screen lines 1 2 128 255 256
8.3.2.2. SL1, SL2 SL1 and SL2 set the number of lines per scrolling screen. The number of lines is SL1 or SL2 plus one. The relationTable 12. Text display mode
W/S Screen First screen block Second screen block
ship between SAD, SL and the display mode is described below.
Third screen block (partitioned screen) Screen configuration example:
First Layer Second Layer SAD1 SAD2 SL1 SL2 SAD3 (see note 1) Set both SL1 and SL2 to L/F + 1 if not using a partitioned screen.
SAD2 SAD1
0
SL1 Character display page 1
SL2 Graphics display page 2
SAD3
Character display page 3 Layer 2 Layer 1
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Table 12. Text display mode (continued)
W/S First Layer SAD1 Upper screen SL1 SAD3 Lower screen (See note 2.) Set both SL1 and SL2 to ((L/F) / 2 + 1). Screen configuration example: Screen Second Layer SAD2 SL2 SAD4 (See note 2.)
SAD2 SAD1
1
SL1 Character display page 1
Graphics display page 2
SAD3 Graphics display page 4 (SAD4) Character display page 3
Layer 1
Layer 2
Notes: 1. SAD3 has the same value as either SAD1 or SAD2, whichever has the least number of lines (set by SL1 and SL2). 2. Since the parameters corresponding to SL3 and SL4 are fixed by L/F, they do not have to be set in this mode.
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Table 13. Graphics display mode
W/S First Layer Second Layer SAD1 SAD2 Two-layer composition SL1 SL2 SAD3 (see note 3.) Set both SL1 and SL2 to Upper screen L/F + 1 if not using a partitioned screen Screen configuration example:
SAD2 SAD1
Screen
Third Layer --
--
0
SL1 Character display page 1
SL2 Graphics display page 2
SAD3
Character display page 3
Layer 1
Layer 2
Three-layer configuration
SAD1 SL1 = L/F + 1 Screen configuration example:
SAD2 SL2 = L/F + 1
SAD3 --
SAD3 SAD2 SAD1 SL2
Graphics display page 3
0
SL1 Graphics display page 1
Graphics display page 2
Layer 1
Layer 3 Layer 2
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Table 13. Graphics display mode (continued)
W/S First Layer Second Layer SAD1 SAD2 Upper screen SL1 SL2 SAD3 SAD4 Lower screen (See note 2.) (See note 2.) Set both SL1 and SL2 to ((L/F) / 2 + 1). Screen configuration example (See note 3.): Screen Third Layer -- --
SAD2 SAD1
1
SL1 Graphics display page 1
Graphics display page 2
SAD3 Graphics display page 4 Graphics display page 3
Layer 1
Layer 2
Notes: 1. SAD3 has the same value as either SAD1 or SAD2, whichever has the least number of lines (set by SL1 and SL2). 2. Since the parameters corresponding to SL3 and SL4 are fixed by L/F, they do not have to be set. 3. If, and only if, W/S = 1, the differences between SL1 and (L/F + 1) / 2, and between SL2 and (L/F + 1) / 2, are blanked.
SL1
Upper Panel
L Lower Panel L/2 Graphics
Figure 12. Two-panel display height
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8.3.3. CSRFORM
Sets the cursor size and shape. Although the cursor is normally only used in text displays, it may also be used in graphics displays when displaying special characters.
MSB C P1 P2 0 0 CM 1 0 0 0 0 0 1 0 0 1 1 0 LSB 1
Character start point 0 1 2 3 4
X3 CRX X2 X1 X0 CRY Y2 Y1 Y0
0123456*
*
*
5 6
Y3
7 8 9 CRX = 5 dots CRY = 9 dots CM = 0
Figure 13. CSRFORM parameter bytes 8.3.3.1. CRX Sets the horizontal size of the cursor from the character origin. CRX is equal to the cursor size less one. CRX must be less than or equal to FX. Table 14. Horizontal cursor size selection
CRX HEX X3 X2 X1 X0 0 0 0 0 0 1 4 E F 0 0 1 1 0 1 1 1 0 0 1 1 1 0 0 1 [CRX] cursor width (pixels) 1 2 9 15 16
Figure 14. Cursor size and position 8.3.3.3. CM Sets the cursor shape. Always set CM to 1 when in graphics mode. CM = 0: Underscore cursor CM = 1: Block cursor
8.3.4. CSRDIR
Sets the direction of automatic cursor increment. The cursor can move left or right one character, or up or down by the number of bytes specified by the address pitch, AP. When reading from and writing to display memory, this automatic cursor increment controls the display memory address increment on each read or write.
MSB C 0 1 0 0 1 1 LSB CD1 CD2
8.3.3.2. CRY Sets the location of an underscored cursor in lines, from the character origin. When using a block cursor, CRY sets the vertical size of the cursor from the character origin. CRY is equal to the number of lines less one. Table 15. Cursor height selection
HEX 0 1 8 E F CRY Y3 Y2 Y1 Y0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 1
Figure 15. CSRDIR parameters
10
[CRY] cursor height (lines) Illegal 2 9 15 16
-1 01
-AP
+1 00
+AP 11
Figure 16. Cursor direction
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Table 16. Cursor shift direction
C 4CH 4DH 4EH 4FH CD1 0 0 1 1 CD0 0 1 0 1 Shift direction Right Left Up Down
Note: Since the cursor moves in address units even if FX 9, the cursor address increment must be preset for movement in character units. See Section 9.3.
8.3.5. OVLAY
Selects layered screen composition and screen text/ graphics mode.
MSB C P1 0 0 1 0 0 0 1 1 0 1 LSB 1
OV DM2 DM1 MX1 MX0
Figure 17. OVLAY parameters 8.3.5.1. MX0, MX1 MX0 and MX1 set the layered screen composition method, which can be either OR, AND, Exclusive-OR or PriorityOR. Since the screen composition is organized in layers and not by screen blocks, when using a layer divided into two screen blocks, different composition methods cannot be specified for the individual screen blocks. The Priority-OR mode is the same as the OR mode unless flashing of individual screens is used. Table 17. Composition method selection
MX1 0 0 1 1
Notes: L1: First layer (text or graphics). If text is selected, layer L3 cannot be used. L2: Second layer (graphics only) L3: Third layer (graphics only)
MX0 0 1 0 1
Function L1 L2 L3 (L1 L2) L3 (L1 L2) L3 L1 > L2 > L3
Composition Method OR Exclusive-OR AND Priority-OR
Applications Underlining, rules, mixed text and graphics Inverted characters, flashing regions, underlining Simple animation, three-dimensional appearance
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Layer 1 1
Layer 2
Layer 3
Visible display
EPSON
EPSON OR
2
EPSON
EPSON Exclusive OR
3
EPSON
SON AND
4
EPSON
Figure 18. Combined layer display
EPSON Prioritized OR
Notes: L1: Not flashing L2: Flashing at 1 Hz L3: Flashing at 2 Hz
8.3.5.2. DM1, DM2 DM1 and DM2 specify the display mode of screen blocks 1 and 3, respectively. DM1/2 = 0: Text mode DM1/2 = 1: Graphics mode Note 1: Screen blocks 2 and 4 can only display graphics. Note 2: DM1 and DM2 must be the same, regardless of the setting of W/S.
8.3.5.3. OV Specifies two- or three-layer composition in graphics mode. OV = 0: Two-layer composition OV = 1: Three-layer composition Set OV to 0 for mixed text and graphics mode.
8.3.6. CGRAM ADR
Specifies the CG RAM start address.
MSB C P1 P2 0 A7 1 A6 0 A5 1 A4 1 A3 1 A2 0 A1 A9
LSB 0 A0 (SAGL) A8 (SAGH)
A15 A14 A13 A12 A11 A10
Figure 19. CGRAM ADR parameters Note See section 10 for information on the SAG parameters.
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8.3.7. HDOT SCR
While the SCROLL command only allows scrolling by characters, HDOT SCR allows the screen to be scrolled horizontally by pixels. HDOT SCR cannot be used on individual layers.
MSB C P1 0 0 1 0 0 0 1 0 1 0 0 D2 1 D1 LSB 0 D0
Table 18. Scroll step selection (continued)
P1 HEX 00 01 02 06 07
M
D2 D1 D0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 1
Number of pixels to scroll 0 1 2 6 7
Figure 20. HDOT SCR parameters 8.3.7.1. D0 to D2 Specifies the number of pixels to scroll. The C/R parameter has to be set to one more than the number of horizontal characters before using HDOT SCR. Smooth scrolling can be simulated if the controlling microprocessor repeatedly issues the HDOT SCR command to the S1D13305 series. See Section 9.5 for more information on scrolling the display.
A
B
X
Y
Z
A
B
X
Y
M=0 N=0
Z
A
B Display width
X N
Y
M/N is the number of bits (dots) that parameter 1 (P1) is incremented/decremented by.
Figure 21. Horizontal scrolling
8.4. Drawing Control Commands
8.4.1. CSRW
The 16-bit cursor address register contains the display memory address of the data at the cursor position as shown in Figure 22. Note that the microprocessor cannot directly access the display memory. The MREAD and MWRITE commands use the address in this register.
MSB C P1 P2 0 A7 1 A6 0 A5 0 A4 0 A3 1 A2 1 A1 A9
LSB 0 A0 (CSRL) A8 (CSRH)
A15 A14 A13 A12 A11 A10
Figure 22. CSRW parameters
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The cursor address register can only be modified by the CSRW command, and by the automatic increment after an MREAD or MWRITE command. It is not affected by display scrolling.
If a new address is not set, display memory accesses will be from the last set address or the address after previous automatic increments.
8.4.2. CSRR
Reads from the cursor address register. After issuing the command, the data read address is read twice, for the low byte and then the high byte of the register.
MSB C P1 P2 0 A7 1 A6 0 A5 0 A4 0 A3 1 A2 1 A1 A9 LSB 1 A0 (CSRL) A8 (CSRH)
A15 A14 A13 A12 A11 A10
Figure 23. CSRR parameters
8.5. Memory Control Commands
8.5.1. MWRITE
The microprocessor may write a sequence of data bytes to display memory by issuing the MREAD command and then writing the bytes to the S1D13305 series. There is no need for further MWRITE commands or for the microMSB C P1 P2 0 1 0 0 0 0 1
processor to update the cursor address register after each byte as the cursor address is automatically incremented by the amount set with CSRDIR, in preparation for the next data write.
LSB 0
Pn
n1
Figure 24. MWRITE parameters
Note: P1, P2, ..., Pn: display data.
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8.5.2. MREAD
Puts the S1D13305 series into the data output state. Each time the microprocessor reads the buffer, the cursor address is incremented by the amount set by CSRDIR and the next data byte fetched from memory, so a sequence of data bytes may be read without further MREAD commands or by updating the cursor address register. If the cursor is displayed, the read data will be from two positions ahead of the cursor.
MSB C P1 P2 0 1 0 0 0 0 1
LSB 1
Pn
n1
Figure 25. MREAD parameters
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9. DISPLAY CONTROL FUNCTIONS
9.1. Character Configuration
The origin of each character bitmap is in the top left corner as shown in Figure 29. Adjacent bits in each byte are horizontally adjacent in the corresponding character image.
Character starting point FX R0 R1 R2 Character height R3 R4 R5 R6 FY R7 R8 R9 R10 Space R11 R12 R13 R14 R15 Character width Space D7 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 to 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Space data D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Space data
Although the size of the bitmap is fixed by the character generator, the actual displayed size of the character field can be varied in both dimensions.
Figure 26. Example of character display ([FX] 8) and generator bitmap If the area outside the character bitmap contains only zeros, the displayed character size can easily be increased by increasing FX and FY, as the zeros ensure that the extra space between displayed characters is blank. The displayed character width can be set to any value up to 16 even if each horizontal row of the bitmap is two bytes wide.
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FX
Horizontal non-display area
Character Height
FY
16 dots Space
Vertical non-display area
8 dots
8 dots
Character width
Space
Figure 27. Character width greater than one byte wide ([FX] = 9)
Note: The S1D13305 series does not automatically insert spaces between characters. If the displayed character size is 8 pixels or less and the space between character origins is nine pixels or more, the bitmap must use two bytes per row, even though the character image requires only one.
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9.2. Screen Configuration
9.2.1. Screen configuration
The basic screen configuration of the S1D13305 series is as a single text screen or as overlapping text and graphics screens. The graphics screen uses eight times as much display memory as the text screen. Figure 28 shows the relationship between the virtual screens and the physical screen.
A/P 0000H C/R Character memory area 0800H 07FFH
Graphics memory area
Display memory window
47FFH (0,YM) (XW,YM) (X,Y) Y (0,0) X (XM,0) (XM,YM)
Figure 28. Virtual and physical screen relationship
9.2.2. Display address scanning
The S1D13305 series scans the display memory in the same way as a raster scan CRT screen. Each row is scanned from left to right until the address range equals C/R. Rows are scanned from top to bottom. In graphics mode, at the start of each line, the address counter is set to the address at the start of the previous line plus the address pitch, AP. In text mode, the address counter is set to the same start address, and the same character data is read, for each row in the character bitmap. However, a new row of the character generator output is used each time. Once all the rows in the character bitmap have been displayed, the address counter is set to the start address plus AP and the next line of text is displayed.
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1 * * * 8 9 * * * 16 17 * * * 24 * * * *
SAD
SAD + 1
SAD + 2
SAD + C/R
SAD + AP
SAD + AP +1
SAD + AP +2
SAD + AP + C/R
SAD + 2AP
C/R W/S = 0, FX = 8, FY = 8
Figure 29. Character position parameters
Note: One byte of display memory corresponds to one character.
1 2 3 * * * * * * * *
SAD SAD + AP SAD + 2AP
SAD +1 SAD + AP +1
SAD + 2 SAD + AP +2
SAD + C/R SAD + AP + C/R Line 1
SAD SAD +1 SAD + 2 AP SAD + C/R SAD + AP SAD + AP + 1 AP SAD + AP + C/R SAD + 2AP
Line 2
Line 3
C/R W/S = 0, FX = 8
Figure 30. Character parameters vs. memory
Note: One bit of display memory corresponds to one pixel.
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1 * * * 8 9 * * * 16 17 * * * 24 25 * * * (L/F)/2 = +1 * * * +8 +9 * * * + 16 + 17 * * * + 24 + 25 * * * * (L/F)
SAD1
SAD1 + 1
SAD1 + 2
SAD1 + C/R
SAD1 + AP
SAD1 + AP +1
SAD1 + AP +2
SAD1 + AP + C/R
SAD1 + 2AP
SAD3 + 1
SAD3 + 2
SAD3 + C/R
SAD3 + AP
SAD3 + AP +1
SAD3 + AP +2
SAD3 + AP + C/R
SAD3 + 2AP
C/R W/S = 1, FX = 8, FY = 8
Figure 31. Two-panel display address indexing Note In two-panel drive, the S1D13305 series reads line 1 and line + 1 as one cycle. The upper and lower panels are thus read alternately, one line at a time.
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9.2.3. Display scan timing
Figure 32 shows the basic timing of the S1D13305 series. One display memory read cycle takes nine periods of the system clock, 0 (fOSC ). This cycle repeats (C/R + 1) times per display line. When reading, the display memory pauses at the end of each line for (TC/R - C/R) display memory read cycles,
0
T0 T1 Display read cycle interval T2
though the LCD drive signals are still generated. TC/R may be set to any value within the constraints imposed by C/R, fOSC , fFR , and the size of the LCD panel, and it may be used to fine tune the frame frequency. The microprocessor may also use this pause to access the display memory data.
VCE
Character read interval Graphics read interval Character generator read interval
VA
Figure 32. Display memory basic read cycle
Display period TC/R C/R
Divider frequency period
Line 1 2 Frame period 3
O O O
R R R
* * * * *
(L/F) O R LP
Figure 33. Relationship between TC/R and C/R
Note: The divider adjustment interval (R) applies to both the upper and lower screens even if W/S = 1. In this case, LP is active only at the end of the lower screen's display interval.
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9.3. Cursor Control
9.3.1. Cursor register function
The S1D13305 series cursor address register functions as both the displayed cursor position address register and the display memory access address register. When accessing display memory outside the actual screen memory, the address register must be saved before accessing the memory and restored after memory access is complete.
Cursor display address register Cursor register Address pointer
Although the cursor is normally displayed for character data, the S1D13305 series may also display a dummy cursor for graphical characters. This is only possible if the graphics screen is displayed, the text screen is turned off and the microprocessor generates the cursor control address.
D=1 FC1 = 0 Cursor ON FC0 = 1
Figure 34. Cursor addressing Note that the cursor may disappear from the display if the cursor address remains outside the displayed screen memory for more than a few hundred milliseconds.
FP1 = 0 FP0 = 0 Block screen 1 (character screen) OFF
9.3.2. Cursor movement
On each memory access, the cursor address register changes by the amount previously specified with CSRDIR, automatically moving the cursor to the desired location.
FP3 = 0 FP2 = 1
Block screen 2 (graphics screen) ON
9.3.3. Cursor display layers
Although the S1D13305 series can display up to three layers, the cursor is displayed in only one of these layers: Two-layer configuration: First layer (L1) Three-layer configuration: Third layer (L3) The cursor will not be displayed if it is moved outside the memory for its layer. Layers may be swapped or the cursor layer moved within the display memory if it is necessary to display the cursor on a layer other than the present cursor layer.
Figure 35. Cursor display layers Consider the example of displaying Chinese characters on a graphics screen. To write the display data, the cursor address is set to the second screen block, but the cursor is not displayed. To display the cursor, the cursor address is set to an address within the blank text screen block. Since the automatic cursor increment is in address units, not character units, the controlling microprocessor must set the cursor address register when moving the cursor over the graphical characters.
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8 dots 8 dots
8 dots 8 dots Block cursor
18 dots
Auto shift
Auto shift
Auto shift
Cursor address preset
Figure 36. Cursor movement If no text screen is displayed, only a bar cursor can be displayed at the cursor address. If the first layer is a mixed text and graphics screen and the cursor shape is set to a block cursor, the S1D13305 series automatically decides which cursor shape to display. On the text screen it displays a block cursor, and on the graphics screen, a bar cursor.
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9.4. Memory to Display Relationship
The S1D13305 series supports virtual screens that are larger than the physical size of the LCD panel address range, C/R. A layer of the S1D13305 series can be considered as a window in the larger virtual screen held in display memory. This window can be divided into two blocks, with each block able to display a different portion of the virtual screen. This enables, for example, one block to dynamically scroll through a data area while the other acts as a status message display area. See Figure 37 and 38.
AP W/S = 0 SAD1 SAD3 Display page 1 SAD2 Layer 1 Display page 2 Layer 2 SAD1 SAD1 Display page 1 SAD3 Display page 3 Layer 1 SAD2 SAD2 Display page 2 Layer 2 SAD3 C/R Graphics page 3 Graphics page 2 C/R C/R SAD3 Character page 3 SAD4 Graphics page 2 Graphics page 2 C/R SAD2 SAD4 C/R Character page 1 Character page 3 SAD1 SAD3 W/S = 1 Display page 1 Display page 3 Layer 1 Display page 2 Display page 4 Layer 2 CG RAM C/R Character page 1
SAD3 SAD2 SAD1 Display page 3 Display page 2 Display page 1 SAD1 Layer 1 Layer 2 Layer 3 SAD2
C/R Graphics page 2
C/R Graphics page 1
Figure 37. Display layers and memory
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AP 0000H
SAD1
FX
FY
CRY
CSRA L/F
CRX
Display window
Virtual display memory limit
C/R
FX = Horizontal character field 16 dots FY = Vertical character field 16 dots CRX = Horizontal cursor size 16 dots CRY = Vertical cursor size 16 dots C/R = Characters per row 240 bytes L/F = Lines per frame 256 bytes AP = Address pitch 64 Kbytes
FFFFH
Figure 38. Display window and memory
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50
SAD1 0000 SL1 0300 0400 C Page 2 0800 SAD2 SL2 Y 02FF 0080 (MSB) D7 (LSB)(MSB) D0 D7 (LSB) D0 Page 2 4440 SAG 4800 Character generator RAM 4A00 Not used F000 HEX D7 D0 1FFF 2000 2800 Page 1 X Display XY B Page 1 A (Code) ABC 0000 D7 to D0 D7 to D0 Character generator ROM 70 88 88 88 F8 88 88 00 01110000 10001000 10001000 10001000 11111000 10001000 10001000 00000000 #4800 1 2 3 4 5 6 #4807 Example of character A Magnified image
DISPLAY CONTROL FUNCTIONS
Character code
Back layer
Figure 39. Memory map and magnified characters
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9.5. Scrolling
The controlling microprocessor can set the S1D13305 series scrolling modes by overwriting the scroll address registers SAD1 to SAD4, and by directly setting the scrolling mode and scrolling rate. Since the S1D13305 series does not automatically erase the bottom line, it must be erased with blanking data when changing the scroll address register.
9.5.1. On-page scrolling
The normal method of scrolling within a page is to move the whole display up one line and erase the bottom line.
Display memory AP C/R ABC WXYZ 789 SAD1 ABC WXYZ 789
Before scrolling
SAD3 After scrolling WXYZ 789 SAD1 WXYZ 789
Blank
Blank
Figure 40. On-page scrolling
9.5.2. Inter-page scrolling
Scrolling between pages and page switching can be performed only if the display memory capacity is greater than one screen.
Display memory AP C/R ABC WXYZ 789 SAD1 ABC WXYZ 789
Before scrolling
After scrolling
WXYZ
789
SAD1
ABC WXYZ 789
Figure 41. Inter-page scrolling
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9.5.3. Horizontal scrolling
The display can be scrolled horizontally in one-character units, regardless of the display memory capacity.
Display Before scrolling ABC 123 XYZ SAD1
Display memory ABC 123 XYZ
AP C/R
After scrolling
BC 23
XYZ1
SAD1
ABC 123
XYZ
Figure 42. Horizontal wraparound scrolling
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9.5.4. Bidirectional scrolling
Bidirectional scrolling can be performed only if the display memory is larger than the physical screen both horizontally and vertically. Although scrolling is normally done in single-character units, the HDOT SCR command can be used to scroll horizontally in pixel units. Single-pixel scrolling both horizontally and vertically can be performed by using the SCROLL and HDOT SCR commands. See Section 16.4
Display memory BC EFG TUV AP A BC EFG TUV
Before scrolling
12
C/R
12 34 567 89
After scrolling
FG TUV
ABC E FG TUV 1234 56 1234 56 7 89
Figure 43. Bidirectional scrolling
9.5.5. Scroll units
Tale 19. Scroll units
Mode Text Graphics Vertical Characters Pixels Horizontal Pixels or characters Pixels
Note that in a divided screen, each block cannot be independently scrolled horizontally in pixel units.
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10. CHARACTER GENERATOR
10.1. CG Characteristics
10.1.1. Internal character generator
The internal character generator is recommended for minimum system configurations containing a S1D13305 series, display RAM, LCD panel, single-chip microprocessor and power supply. Since the internal character generator uses a CMOS mask ROM, it is also recommended for low-power applications. * 5 x 7-pixel font (See Section 17.) * 160 JIS standard characters * Can be mixed with character generator RAM (maximum of 64 CG RAM characters) * Can be automatically spaced out up to 8 x 16 pixels
10.1.3. Character generator RAM
The user can freely use the character generator RAM for storing graphics characters. The character generator RAM can be mapped by the microprocessor anywhere in display memory, allowing effective use of unused address space. * Up to 8 x 8-pixel characters (M2 = 0) or 8 x 16 characters (M2 = 1) * Up to 256 characters if mapped at F000H to FFFFH (64 if used together with character generator ROM) * Can be mapped anywhere in display memory address space if used with the character generator ROM * Mapped into the display memory address space at F000H to F7FFH if not used with the character generator ROM (more than 64 characters are in the CG RAM). Set SAG0 to F000H and M1 to zero when defining characters number 193 upwards.
10.1.2. External character generator ROM
The external CG ROM can be used when fonts other than those in the internal ROM are needed. Data is stored in the external ROM in the same format used in the internal ROM. (See Section 10.3.) * Up to 8 x 8-pixel characters (M2 = 0) or 8 x 16-pixel characters (M2 = 1) * Up to 256 characters (192 if used together with the internal ROM) * Mapped into the display memory address space at F000H to F7FFH (M2 = 0) or F000H to FFFFH (M2 = 1) * Characters can be up to 8 x 16-pixels; however, excess bits must be set to zero.
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10.2. CG Memory Allocation
Since the S1D13305 series uses 8-bit character codes, it can handle no more than 256 characters at a time. However, if a wider range of characters is required, character
Built-in CG ROM (160 characters, 5 x 7 pixels max)
generator memory can be bank-switched using the CGRAM ADR command.
CG RAM n CG RAM 2
SAG
M0 = 1
CG RAM
CG RAM 1
(64 characters max, 8 x 16 pixels max) Basic CG space (256 characters, 8 x 16 pixels max)
CG RAM CG ROM
M0 = 1 Built-in CG ROM (160 characters, 5 x 7 pixels max) CG RAM ADR
256 characters max M1 = 0
256 characters max M1 = 0
CG RAM n CG RAM 2
CG RAM
CG RAM 1
(64 characters max, 8 x 16 pixels max)
Figure 44. Internal and external character mapping
Note that there can be no more than 64 characters per bank.
Table 20. Character mapping
Item Internal/external character generator selection 1 to 8 pixels Character field height 9 to 16 pixels Greater than 16 pixels M0 M2 = 0 M2 = 1 Graphics mode (8 bits x 1 line) Automatic M1 Specified with CG RAM ADR Can be moved anywhere in the command display memory address space Other than the area of Figure 49 Set SAG to F000H and overly SAG and the CG ROM table Determined by the character code Parameter Remarks
Internal CG ROM/RAM select External CG ROM/RAM select CG RAM bit 6 correction CG RAM data storage address External CG ROM address 192 characters or less More than 192 characters
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10.3. Setting the Character Generator Address
The CG RAM addresses in the VRAM address space are not mapped directly from the address in the SAG register. The data to be displayed is at a CG RAM address calculated from SAG + character code + ROW select address. This mapping is shown in Table 21 and 22.
Table 21. Character fonts, number of lines 8 (M2 = 0, M1 = 0)
SAG Character code +ROW select address CG RAM address
A15 A14 A13 A12 A11 A10
A9 D6 0
A8 D5 0
A7 D4 0
A6 D3 0
A5 D2 0
A4 D1 0
A3 D0 0
A2 0 R2
A1 0 R1
A0 0 R0
0 0
0 0
0 0
0 0
0 0
D7 0
VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0
Table 22. Character fonts, 9 number of lines 16 (M2 = 1, M1 = 0)
SAG Character code +ROW select address CG RAM address
Row Row 0 Row 1 Row 2 R3 0 0 0 R2 0 0 0 R1 0 0 1
A15 A14 A13 A12 A11 A10
0 0
0 0
0 0
0 0
D7 0
D6 0
A9 D5 0
A8 D4 0
A7 D3 0
A6 D2 0
A5 D1 0
A4 D0 0
A3 0 R3
A2 0 R2
A1 0 R1
A0 0 R0
VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0
R0 0 1 0
Line 1
Line 2
Row 7 Row 8 0 1 1 0 1 0 1 0
Row 14 Row 15
1 1
1 1
1 1
0 1
Figure 45. Row select address
Note: Lines = 1: lines in the character bitmap 8 Lines = 2: lines in the character bitmap 9
10.3.1. M1 = 1
The S1D13305 series automatically converts all bits set in bit 6 of character code for CG RAM 2 to zero. Because of this, the CG RAM data areas become contiguous in display memory. When writing data to CG RAM: * Calculate the address as for M1 = 0. * Change bit 6 of the character code from "1" to "0".
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10.3.2. CG RAM addressing example
* Define a pattern for the "A" in Figure 26. * The CG RAM table start address is 4800H. * The character code for the defined pattern is 80H (the first character code in the CG RAM area). As the character code table in Figure 46 shows, codes 80H to 9FH and E0H to FFH are allocated to the CG RAM Table 23. Character data example and can be used as desired. 80H is thus the first code for CG RAM. As characters cannot be used if only using graphics mode, there is no need to set the CG RAM data.
CGRAM AD P1 P2 CSRDIR CSRW P1 P2 MWRITE P P2 P3 P4 P5 P6 P7 P8 P8 P16
5CH 00H 40H 4CH 46H 00H 48H 42H 70H 88H 88H 88H F8H 88H 88H 00H 00H 00H Reverse the CG RAM address calculation to calculate SAG Set cursor shift direction to right CG RAM start address is 4800H
Write ROW 0 data Write ROW 1 data Write ROW 2 data Write ROW 3 data Write ROW 4 data Write ROW 5 data Write ROW 6 data Write ROW 7 data Write ROW 8 data Write ROW 15 data
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10.4. Character Codes
The following figure shows the character codes and the codes allocated to CG RAM. All codes can be used by the CG RAM if not using the internal ROM.
Upper 4 bits Lower 4 bits 0 1 2 3 4 5 6 7 8 9 A B C D E F ! " # $ 0 1 2 3 4 5 6 ' a b c d e f 7 p q r s t u v w x y z { | } 8 9 A B CD E F
0@P 1 2 3 4 AQ B C D E F R S T U V
%5 & ' ( ) * + , . / 6 7 8 9 : ; < = > ?
GWg H I J K L M N O X Y Z [ ] ^ _ h i j k l m
n o CG RAM1 M1 = 0 M1 = 1 CG RAM2
Figure 46. On-chip character codes
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MICROPROCESSOR INTERFACE
11. MICROPROCESSOR INTERFACE
11.1. System Bus Interface
SEL1, SEL2, A0, RD, WR and CS are used as control signals for the microprocessor data bus. A0 is normally connected to the lowest bit of the system address bus. SEL1 and SEL2 change the operation of the RD and WR pins to enable interfacing to either an 8080 or 6800 family bus, and should have a pull-up or pull-down resistor. With microprocessors using an 8080 family interface, the S1D13305 series is normally mapped into the I/O address space. Display flicker may occur if there is more than one consecutive access that cannot be ignored within a frame. The microprocessor can minimize this either by performing these accesses intermittently, or by continuously checking the status flag (D6) and waiting for it to become HIGH.
11.2.1. Display status indication output
When CS, A0 and RD are LOW, D6 functions as the display status indication output. It is HIGH during the TV-mode vertical retrace period or the LCD-mode horizontal retrace period, and LOW, during the period the controller is writing to the display. By monitoring D6 and writing to the data memory only during retrace periods, the display can be updated without causing screen flicker.
11.1.1. 8080 series
Table 24. 8080 series interface signals A0 RD WR Function 0 0 1 Status flag read Display data and cursor address 1 0 1 read 0 1 0 Display data and parameter write 1 1 0 Command write
11.2.2. Internal register access
The SYSTEM SET and SLEEP IN commands can be used to perform input/output to the S1D13305 series independently of the system clock frequency. These are the only commands that can be used while the S1D13305 series is in sleep mode.
11.1.2. 6800 series
Table 25. 6800 series interface signals A0 R/W E Function 0 1 1 Status flag read Display data and cursor address 1 1 1 read 0 0 1 Display data and parameter write 1 0 1 Command write
11.2.3. Display memory access
The S1D13305 series supports a form of pipelined processing, in which the microprocessor synchronizes its processing to the S1D13305 series timing. When writing, the microprocessor first issues the MWRITE command. It then repeatedly writes display data to the S1D13305 series using the system bus timing. This ensures that the microprocessor is not slowed down even if the display memory access times are slower than the system bus access times. See Figure 47. When reading, the microprocessor first issues the MREAD command, which causes the S1D13305 series to load the first read data into its output buffer. The microprocessor then reads data from the S1D13305 series using the system bus timing. With each read, the S1D13305 series reads the next data item from the display memory ready for the next read access. See Figure 48.
11.2. Microprocessor Synchronization
The S1D13305 series interface operates at full bus speed, completing the execution of each command within the cycle time, tCYC . The controlling microprocessor's performance is thus not hampered by polling or handshaking when accessing the S1D13305 series.
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tCYC WR Microprocessor D0 to D7 Command write Data write Data write
VR/W VRW Display memory VD0 to VD7
Figure 47. Display memory write cycle
WR Command write Microprocessor RD Data read D0 to D7 Data read tCYC
VR/W
VRW
Display memory VD0 to VD7
Figure 48. Display memory read cycle Note A possible problem with the display memory read cycle is that the system bus access time, tACC, does not depend on the display memory access time, tACV. The microprocessor may only make repeated reads if the read loop time exceeds the S1D13305 series cycle time, tCYC. If it does not, NOP instructions may be inserted in the program loop. tACC, tACV and tCYC limits are given in section 6.2.
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11.3. Interface Examples
11.3.1. Z80 to S1D13305 series interface
IORQ A0 A1 to A15 Z80(R) D0 to D7 RD WR RESET RESET
A0
Decoder
CS
D0 to D7 RD WR RES
S1D13305 series
SEL 1 SEL 2
Figure 49. Z80(R) to S1D13305 series interface
Note: Z80(R) is a registered trademark of Zilog Corporation.
11.3.2. 6802 to S1D13305 series interface
VMA A0 A1 to A15 6802 D0 to D7 E R/W RESET RESET
A0
Decoder
CS S1D13305 series VDD SEL 1 SEL 2
D0 to D7 RD WR RES
Figure 50. 6802 to S1D13305 series interface
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DISPLAY MEMORY INTERFACE
12. DISPLAY MEMORY INTERFACE
12.1. Static RAM
The figure below shows the interface between an 8K x 8 static RAM and the S1D13305 series. Note that bus buffers are required if the bus is heavily loaded. * S1D13305F
Note VA0 to VA12 HC138 VA13 to VA15 A-C Y VDD S1D13305 CE2 2764-pin compatible memory CE1 A0 to A12
WRD VWR VD0 to VD7 Note
OE WE I/O1 to I/O8
Figure 51. Static RAM interface Note: If the bus load is too much, use a bus buffer.
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DISPLAY MEMORY INTERFACE/OSCILLATOR CIRCUIT/STATUS FLAG
12.2. Supply Current during Display Memory Access
The 24 address and data lines of the S1D13305 series cycle at one-third of the oscillator frequency, fOSC. The charge and discharge current on these pins, IVOP, is given by the equation below. When IVOP exceeds IOPR, it can be estimated by: IVOP C V f where C is the capacitance of the display memory bus, V is the operating voltage, and f is the operating frequency. If VOPR = 5.0V, f = 1.0 MHz, and the display memory bus capacitance is 1.0 pF per line: IVOP 120 A / MHz x pF To reduce current flow during display memory accesses, it is important to use low-power memory, and to minimize both the number of devices and the parasitic capacitance.
13. OSCILLATOR CIRCUIT
The S1D13305 series incorporates an oscillator circuit. A stable oscillator can be constructed simply by connecting an AT-cut crystal and two capacitors to XG and XD, as shown in the figure below. If the oscillator frequency is increased, CD and CG should be decreased proportionally. Note that the circuit board lines to XG and XD must be as short as possible to prevent wiring capacitance from changing the oscillator frequency or increasing the power consumption.
S1D13305 series
XG CG
XD
CD = 3 to 20 pF
CD
CG = 2 to 18 pF Load impedance = 700 (max)
Figure 52. Crystal oscillator
14. STATUS FLAG
The S1D13305 series has a single bit status flag. D6: X line standby
D7 X D6 X X X X X D0 X X: Don't care
The D6 status flag is HIGH for the TC/R-C/R cycles at the end of each line where the S1D13305 series is not reading the display memory. The microprocessor may use this period to update display memory without affecting the display, however it is recommended that the display be turned off when refreshing the whole display.
Figure 53. Status flag
LP tTC/R tm XSCL tC/R
Figure 54. C/R to TC/R time difference
CS 0
A0 0
RD 0
D6 (flag) 0: Period of retrace lines 1: Period of display
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STATUS FLAG
Read Status Flag
No
D6 = 0?
Yes Data Input
No Data Input ?
Yes
Figure 55. Flowchart for busy flag checking

* Precaution on the write timing to VRAM
The allowable writing duration is since "5 x 9 x tOSC" has elapsed (tOSC = 1/fOSC: a cycle of the oscillation frequency) from the positive going edge of LP up to {(TCR) - (C/R) - 7} x 9 x tOSC. Currently employed D6 status flag reading method does not identify the timing when the read D6 = Low took place. Thus, negative going edge of LP should be used as the interrupt signal when implementing the writing in above timing. If you try to access the display memory in other timing than the above, flickering of the display screen will result.
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RESET/APPLICATION NOTES
15. RESET
VDD
1ms reset pulse RES 0.7 VDD 0.3 VDD
Figure 56. Reset timing The S1D13305 series requires a reset pulse at least 1 ms long after power-on in order to re-initialize its internal state. For maximum reliability, it is not recommended to apply a DC voltage to the LCD panel while the S1D13305 series is reset. Turn off the LCD power supplies for at least one frame period after the start of the reset pulse. The S1D13305 series cannot receive commands while it is reset. Commands to initialize the internal registers should be issued soon after a reset. During reset, the LCD drive signals XD, LP and FR are halted. A delay of 3 ms (maximum) is required following the rising edges of both RES and VDD to allow for system stabilization.
16. APPLICATION NOTES
16.1. Initialization Parameters
The parameters for the initialization commands must be determined first. Square brackets around a parameter name indicate the number represented by the parameter, rather than the value written to the parameter register. For example, [FX] = FX + 1. I TC/R TC/R must satisfy the condition [TC/R] [C/R] + 4. I fOSC and fFR Once TC/R has been set, the frame frequency, fFR, and lines per frame [L/F] will also have been set. The lower limit on the oscillator frequency fOSC is given by: fOSC ([TC/R] x 9 + 1) x [L/F] x fFR I If no standard crystal close to the calculated value of fOSC exists, a higher frequency crystal can be used and the value of TC/R revised using the above equation. I Symptoms of an incorrect TC/R setting are listed below. If any of these appears, check the value of TC/ R and modify it if necessary. * Vertical scanning halts and a high-contrast horizontal line appears. * All pixels are on or off. * The LP output signal is absent or corrupted. * The display is unstable.
16.1.1. SYSTEM SET instruction and parameters
I FX The horizontal character field size is determined from the horizontal display size in pixels [VD] and the number of characters per line [VC]. [VD] / [VC] [FX] I C/R C/R can be determined from VC and FX. [C/R] = RND ([FX] / 8) x [VC] where RND(x) denotes x rounded up to the next highest integer. [C/R] is the number of bytes per line, not the number of characters.
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Table 26. Epson LCD unit example parameters
Product name and resolution (X x Y) 256 x 64 [FX] [FX] = 6 pixels: 256 / 6 = 42 remainder 4 = 4 blank pixels [FX] = 6 pixels: 512 / 6 = 85 remainder 2 = 2 blank pixels [FX] = 8 pixels: 256 / 8 = 32 remainder 0 = no blank pixels [FX] = 10 pixels: 512 / 10 = 51 remainder 2 = 2 blank pixels [FY] 8 or 16, depending on the screen 8 or 16, depending on the screen 8 or 16, depending on the screen 8 or 16, depending on the screen [C/R] [C/R] = 42 = 2AH bytes: C/R = 29H. When using HDOT SCR, [C/R] = 43 bytes [C/R] = 85 = 55H bytes: C/R = 54H. When using HDOT SCR, [C/R] = 86 bytes [C/R] = 32 = 20H bytes: C/R = 19H. When using HDOT SCR, [C/R] = 33 bytes [C/R] = 102 = 66H bytes: C/R = 65H. When using HDOT SCR, [C/R] = 103 bytes TC/R 2DH fOSC (MHz) See Note 2. 1.85
512 x 64
58H
3.59
256 x 128
22H
2.90
512 x 128
69H
8.55
Notes: 1. The remainder pixels on the right-hand side of the display are automatically blanked by the S1D13305F. There is no need to zero the display memory corresponding to these pixels. 2. Assuming a frame frequency of 60 Hz.
16.1.2. Initialization example
The initialization example shown in Figure 57 is for a S1D13305 series with an 8-bit microprocessor interface bus and an Epson EG4810S-AR display unit (512 x 128 pixels).
Start
Clear first memory layer Clear second memory layer CSRW
Supply on
SYSTEM SET
SCROLL
CSR FORM
HDOT SCR
DISP ON Output display data
OVLAY
DISP OFF
Figure 57. Initialization procedure
Note: Set the cursor address to the start of each screen's layer memory, and use MWRITE to fill the memory with space characters, 20H (text screen only) or 00H (graphics screen only). Determining which memory to clear is explained in section 16.1.3.
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Table 27. Initialization procedure
No. 1 2 3 Command Power-up Supply SYSTEM SET C = 40H P1 = 38H Operation
P2 = 87H P3 = 07H P4 = 3FH P5 = 49H P6 = 7FH P7 = 80H P8 = 00H SCROLL C = 44H P1 = 00H P2 = 00H P3 = 40H P4 = 00H P5 = 10H P6 = 40H P7 = 00H P8 = 04H
M0: Internal CG ROM M1: CG RAM is 32 characters maximum M2: 8 lines per character W/S: Two-panel drive IV: No top-line compensation FX: Horizontal character size = 8 pixels WF: Two-frame AC drive FY: Vertical character size = 8 pixels C/R: 64 display addresses per line TC/R: Total address range per line = 90 fOSC = 6.0 MHz, fFR = 70 Hz L/F: 128 display lines AP: Virtual screen horizontal size is 128 addresses
4
First screen block start address Set to 0000H Display lines in first screen block = 64 Second screen block start address Set to 1000H Display lines in second screen block = 64 Third screen block start address Set to 0400H
(continued)
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Table 27. Initialization procedure (continued)
No. Command P9 = 00H P10 = 30H Operation Fourth screen block start address Set to 3000H
Display memory (SAD1) 0000H (SAD3) 0400H 0800H (SAD2) 1000H 3rd display memory page (SAD4) 3000H 4th display memory page 5000H 1st display memory page 2nd display memory page
5
6
HDOT SCR C = 5AH P1 = 00H OVLAY C = 5BH P1 = 01H
Set horizontal pixel shift to zero
MX 1, MX 0: Inverse video superposition DM 1: First screen block is text mode DM 2: Third screen block is text mode D: Display OFF FC1, FC0: Flash cursor at 2 Hz FP1, FP0: First screen block ON FP3, FP2: Second and fourth screen blocks ON FP5, FP4: Third screen block ON Fill first screen layer memory with 20H (space character)
7
DISP ON/OFF C = 58H P1 = 56H
8
(continued)
Clear data in first layer
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Table 27. Initialization procedure (continued)
No. 9 Command Clear data in second layer Operation Fill second screen layer memory with 00H (blank data)
Display Character code in every position
1st layer Blank code in every position
2nd layer
10
11
CSRW C = 46H P1 = 00H P2 = 00H CSR FORM C = 5DH P1 = 04H P2 = 86H DISP ON/OFF C = 59H
Set cursor to start of first screen block
CRX: Horizontal cursor size = 5 pixels CRY: Vertical cursor size = 7 pixels CM: Block cursor Display ON
12
Display
13
(continued)
CSR DIR C = 4CH
Set cursor shift direction to right
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APPLICATION NOTES
Table 27. Initialization procedure (continued)
No. 14 Command MWRITE C = 42H P1 = 20H P2 = 45H P3 = 50H P4 = 53H P5 = 4FH P6 = 4EH Operation
`' `E' `P' `S' `O' `N'
EPSON
15
16 17
CSRW C = 46H P1 = 00H P2 = 10H CSR DIR C = 4FH MWRITE C = 42H P1 = FFH P9 = FFH
Set cursor to start of second screen block
Set cursor shift direction to down
Fill in a square to the left of the `E'
EPSON
18
CSRW C = 46H P1 = 01H P2 = 10H MWRITE C = 42H Set cursor address to 1001H
19
(continued)
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Table 27. Initialization procedure (continued)
No. Command P1 = FFH P9 = FFH CSRW Operation Fill in the second screen block in the second column of line 1
20
Repeat operations 18 and 19 to fill in the background under `EPSON'
Inverse display
29
MWRITE
EPSON
30
31 32
CSRW C = 46H P1 = 00H P2 = 01H CSR DIR C = 4CH MWRITE C = 42H P1 = 44H P2 = 6FH P3 = 74H P4 = 20H P5 = 4DH P6 = 61H P7 = 74H P8 = 72H P9 = 69H P10 = 78H P11 = 20H P12 = 4CH P13 = 43H P14 = 44H
Set cursor to line three of the first screen block
Set cursor shift direction to right
`D' `o' `t' `' `M' `a' `t' `r' `i' `x' `' `L' `C' `D'
Inverse display
EPSON
Dot matrix LCD
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APPLICATION NOTES
16.1.3. Display mode setting example 1: combining text and graphics
I Conditions * 320 x 200 pixels, single-panel drive (1/200 duty cycle) * First layer: text display * Second layer: graphics display * 8 x 8-pixel character font * CG RAM not required I Display memory allocation * First layer (text): 320/8 = 40 characters per line, 200/8 = 25 lines. Required memory size = 40 x 25 = 1000 bytes. * Second layer (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 40 x 200 = 8000 bytes.
03E8H 2nd graphics layer (8000 bytes)
0000H 1st character layer (1000 bytes)
2327H
03E7H
Figure 58. Character over graphics layers I Register setup procedure
SYSTEM SET TC/R calculation C = 40H P1 = 30H fOSC = 6 MHz fFR = 70 Hz P2 = 87H P3 = 07H P4 = 27H (1/6) x 9 x [TC/R] x 200 = 1/70 P5 = 2FH [TC/R] = 48, so TC/R = 2FH P6 = C7H P7 = 28H P8 = 00H SCROLL C = 44H P1 = 00H P2 = 00H P3 = C8H P4 = E8H P5 = 03H P6 = C8H P7 = XH P8 = XH P9 = XH P10 = XH
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APPLICATION NOTES
CSR FORM C = 5DH P1 = 04H P2 = 86H HDOT SCR C = 5AH P1 = 00H
OVLAY C = 5BH P1 = 00H DISP ON/OFF C = 59H P1 = 16H X= Don't care
16.1.4. Display mode setting example 2: combining graphics and graphics
I Conditions * 320 x 200 pixels, single-panel drive (1/ 200 duty cycle) * First layer: graphics display * Second layer: graphics display I Display memory allocation * First layer (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 40 x 200 = 8000 bytes. * Second layer (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 8000 bytes.
1F40H 2nd graphics layer (8000 bytes)
0000H 1st graphics layer (8000 bytes)
3E7FH
1F3FH
Figure 59. Two-layer graphics
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APPLICATION NOTES
I Register setup procedure
SYSTEM SET TC/R calculation C = 40H P1 = 30H fOSC = 6 MHz fFR = 70 Hz P2 = 87H P3 = 07H P4 = 27H (1/6) x 9 x [TC/R] x 200 = 1/70 P5 = 2FH [TC/R] = 48, so TC/R = 2FH P6 = C7H P7 = 28H P8 = 00H SCROLL C = 44H P1 = 00H P2 = 00H P3 = C8H P4 = 40H P5 = 1FH P6 = C8H P7 = XH P8 = XH P9 = XH P10 = XH
CSR FORM C = 5DH P1 = 07H P2 = 87H HDOT SCR C = 5AH P1 = 00H OVLAY C = 5BH P1 = 0CH DISP ON/OFF C = 59H P1 = 16H X = Don't care
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16.1.5. Display mode setting example 3: combining three graphics layers
I Conditions * 320 x 200 pixels, single-panel drive (1/200 duty cycle) * First layer: graphics display * Second layer: graphics display * Third layer: graphics display I Display memory allocation * All layers (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 40 x 200 = 8000 bytes.
3E80H 3rd graphics layer (8000 bytes)
1F40H 2nd graphics layer (8000 bytes)
5DBFH
0000H 1st graphics layer (8000 bytes)
3E7FH
1F3FH
Figure 60. Three-layer graphics I Register setup procedure
SYSTEM SET TC/R calculation C = 40H P1 = 30H fOSC = 6 MHz P2 = 87H fFR = 70 Hz P3 = 07H P4 = 27H (1/6) x 9 x [TC/R] x 200 = 1/70 P5 = 2FH [TC/R] = 48, so TC/R = 2FH P6 = C7H P7 = 28H P8 = 00H SCROLL C = 44H P1 = 00H P2 = 00H P3 = C8H P4 = 40H P5 = 1FH P6 = C8H P7 = 80H P8 = 3EH P9 = XH P10 = XH
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CSR FORM C = 5DH P1 = 07H P2 = 87H HDOT SCR C = 5AH P1 = 00H
OVLAY C = 5BH P1 = 1CH DISP ON/OFF C = 59H P1 = 16H X = Don't care
16.2. System Overview
Figure 61 shows the S1D13305 series in a typical system. The microprocessor issues instructions to the S1D13305 series, and the S1D13305 series drives the LCD panel and may have up to 64KB of display memory. Since all of the
S1D13305 series Character generator External character generator memory
LCD control circuits are integrated onto the S1D13305 series, few external components are required to construct a complete medium- resolution liquid crystal display.
Microprocessor
Display memory address bus
Display address control
Display memory Display memory data bus LCD unit Driver bus
Driver control
Main memory
X driver
X driver
X driver
Data bus Address bus Control bus
Y driver
LCD panel
Figure 61. System block diagram
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APPLICATION NOTES
16.3. System Interconnection
16.3.1. S1D13305F
10MHz crystal HC138 XG A0 A1 to A7 IORQ Microprocessor D0 to D7 RD WR RESET RESET D0 to D7 RD WR RES XD0 to XD3 A0 XD VA13 to VA15 VCE VRD VA0 to VA12 S1D13305F A B C Y7 Y6 to Y0 CS7 CS6 to CS0
Decoder
CS
VA12
A0 to A12 WE (RAM1) D0 to D7 VD0 to VD7 CS1 CS2 OE
A0 to A12 WE (RAM2) D0 to D7 CS1 CS2 OE
A0 to A11 OE (CGROM) D0 to D7 CE
XECL XSCL LP WF YDIS YD YSCL
LAT DI INH FR YSCL POFF Power supply converter V1 LP XSCL ECL D0 to D3 FR EI FR EI
LCD
LP XSCL ECL D0 to D3
V3 V4 V5
VREG
LCD UNIT
Figure 62. System interconnection diagram
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LP XSCL ECL D0 DO to D3
V2
E0
E0
SED1600F FR EI E1 E0
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APPLICATION NOTES
I CG RAM table * Character generator memory can be modified by the external microprocessor * Character sizes up to 8 x 16-pixels (16 bytes per character) * Maximum of 64 characters * Table mapping can be changed I CG ROM table * Used when the internal character generator is not adequate * Can be used in conjunction with the internal character generator and external character generator RAM * Character sizes up to 8 x 16-pixels (16 bytes per character) * Maximum of 256 characters * Fixed mapping at F000H to FFFFH
The S1D13305 series layered screens and flexible scrolling facilities support a range of display functions and reduces the load on the controlling microprocessor when displaying underlining, inverse display, text overlaid on graphics or simple animation. These facilities are supported by the S1D13305 series ability to divide display memory into up to four different areas. I Character code table * Contains character codes for text display * Each character requires 8 bits * Table mapping can be changed by using the scroll start function I Graphics data table * Contains graphics bitmaps * Word length is 8 bits * Table mapping can be changed
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APPLICATION NOTES
16.4. Smooth Horizontal Scrolling
Figure 63 illustrates smooth display scrolling to the left. When scrolling left, the screen is effectively moving to the right, over the larger virtual screen. Instead of changing the display start address SAD and shifting the display by eight pixels, smooth scrolling is achieved by repeatedly changing the pixel-shift parameter of the HDOT SCR command. When the display has been scrolled seven pixels, the HDOT SCR pixel-shift parameter is reset to zero and SAD incremented by one. Repeating this operation at a suitable rate gives the appearance of smooth scrolling.
HDOT SCR parameter SAD
To scroll the display to the right, the reverse procedure is followed. When the edge of the virtual screen is reached, the microprocessor must take appropriate steps so that the display is not corrupted. The scroll must be stopped or the display modified. Note that the HDOT SCR command cannot be used to scroll individual layers.
SAD + 1
SAD + 2
P1 = 00H
Magnified AP
P1 = 01H
SAD = SAD P1 = 02H Display
P1 = 03H
C/R
Virtual screen P1 = 07H
P1 = 00H SAD = SAD + 1
Not visible
Visible
Figure 63. HDOT SCR example
Note: The response time of LCD panels changes considerably at low temperatures. Smooth scrolling under these conditions may make the display difficult to read.
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APPLICATION NOTES
16.5. Layered Display Attributes
S1D13305 series incorporates a number of functions for enhanced displays using monochrome LCD panels. It allows the display of inverse characters, half-intensity menu pads and flashing of selected screen areas. These functions are controlled by the OVLAY and DISP ON/ OFF commands.
Attribute
MX1
MX0
Combined layer display
1st layer display
2ndt layer display
0 Reverse 1 0 Half-tone 1 0 Local flashing 0 0 Ruled line 0 1
1 IV 1 0 ME 1 0 1 0 1 1 RL LINE LINE RL LINE LINE BL Error BL Error Yes, No ME Yes, No EPSON IV EPSON
Figure 64. Layer synthesis A number of means can be used to achieve these effects, depending on the display configuration. These are listed below. Note, however, that not all of these can be used in the one layer at the same time.
16.5.2. Half-tone display
The FP parameter can be used to generate half-intensity display by flashing the display at 17 Hz. Note that this mode of operation may cause flicker problems with certain LCD panels. 16.5.2.1. Menu pad display Turn flashing off for the first layer, on at 17 Hz for the second layer, and combine the screens using the OR function. 1. OVLAY: P1 = 00H 2. DISP ON/OFF: P1 = 34H
16.5.1. Inverse display
The first layer is text, the second layer is graphics. 1. CSRW, CSDIR, MWRITE Write is into the graphics screen at the area to be inverted. 2. OVLAY: MX0 = 1, MX1 = 0 Set the combination of the two layers to ExclusiveOR. 3. DISP ON/OFF: FP0 = FP1 = 1, FP1 = FP3 = 0. Turn on layers 1 and 2.
SAD1 SAD2
Half-tone
AB +
AB
1st layer
2nd layer
Combined layer display
Figure 65. Half-tone character and graphics
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16.5.2.2. Graph display To present two overlaid graphs on the screen, configure the display as for the menu bar display and put one graph on each screen layer. The difference in contrast between the half- and full-intensity displays will make it easy to
distinguish between the two graphs and help create an attractive display. 1. OVLAY: P1 = 00H 2. DISP ON/OFF: P1 = 34H
16.5.3. Flashing areas
16.5.3.1 Small area To flash selected characters, the MPU can alternately write the characters as character codes and blank characters at intervals of 0.5 to 1.0 seconds. 16.5.3.2. Large area Divide both layer 1 and layer 2 into two screen blocks each, layer 2 being divided into the area to be flashed and the remainder of the screen. Flash the layer 2 screen block at 2 Hz for the area to be flashed and combine the layers using the OR function.
ABC
ABC
XYZ
XYZ
Figure 66. Localized flashing
16.6. 16 x 16-dot Graphic Display
16.6.1. Command usage
This example shows how to display 16 x 16-pixel characters. The command sequence is as follows: CSRW Set the cursor address. CSRDIR Set the cursor auto-increment direction. MWRITE Write to the display memory.
16.6.2. Kanji character display
The program for writing large characters operates as follows: 1. The microprocessor reads the character data from its ROM. 2. The microprocessor sets the display address and writes to the VRAM. The flowchart is shown in Figure 69.
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APPLICATION NOTES
A0 = 0 O8 O7 O6 O5 O4 O3 O2 O1 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Scan address A1 to A4 (1) (3) (5) (7) (9) (11) (13) (15) (17) (19) (21) (23) (25) (27) (29) (31) 1st column
A0 = 1 O8 O7 O6 O5 O4 O3 O2 O1 (2) (4) (6) (8) (10) (12) (14) (16) (18) (20) (22) (24) (26) (28) (30) (32) 2nd column CG ROM output
(n) shows the CG ROM data readout order
(Kanji ROM pattern)
(6) (4) (2)
(19) (17) (15) (13) (11) (9) (7) (5) (3) (1) Data held in the microprocessor memory
2nd column memory area
(4) (2)
1st column memory area
(3) (1)
Data written into the S1D13305 display memory
Figure 67. Graphics address indexing
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320 dots
Direction of cursor movement (1) (3) (5) (7) (9) (11) (13) (15) (17) (19) (21) (23) (25) (27) (29) (31) (2) (4) (6) (8) (10) (12) (14) (16) (18) (20) (22) (24) (26) (28) (30) (32)
240 dots
Figure 68. Graphics bit map Using an external character generator ROM, and 8 x 16pixel font can be used, allowing a 16 x 16-pixel character to be displayed in two segments. The external CG ROM EPROM data format is described in Section 9.1. This will allow the display of up to 128, 16 x 16-pixel characters. If CG RAM is also used, 96 fixed characters and 32 bankswitchable characters can also be supported.
Start
Enable cursor downwards movement
Set column 1 cursor address
Write data
Set column 2 cursor address
Write data
End
Figure 69. 16 x 16-dot display flowchart
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INTERNAL CHARACTER GENERATOR FONT
17. INTERNAL CHARACTER GENERATOR FONT
Character code bits 0 to 3 5 6 7 8 9A
0 2 3 4 5 6 7 A B C D 1
1
2
3
4
B
C
D
E
F
Character code bits 4 to 7
Figure 70. On-chip character set Note The shaded positions indicate characters that have the whole 6 x 8 bitmap blackened.
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GLOSSARY OF TERMS
18. GLOSSARY OF TERMS
A AP C CD CG CGRAM ADR CM C/R CRX CRY CSR DIR CSR FORM CSRR CSRW DM FC fFR fOSC FP FX FY G GLC HDOT SCR IV L/F MREAD MWRITE MX OV OVLAY P R RAM ROM SAD SL TC/R VRAM WF W/S Address Address pitch parameter Character display mode Cursor direction of movement parameter Character generator Character generator memory address Cursor display shape parameter Characters per row parameter Horizontal cursor size parameter Vertical cursor size parameter Cursor direction of movement instruction Cursor size, position and type instruction Read cursor address register instruction Write cursor address register instruction Display mode parameter Flashing cursor parameter Frame frequency Oscillator frequency Screen flashing parameter Horizontal character size parameter Vertical character size parameter Graphics display mode Graphic line control unit Horizontal scrolling by pixels instruction Screen origin compensation for inverse display Lines per frame instruction Display memory read instruction Display memory write instruction Screen composition mode Graphics layer select parameter Screen layer mode instruction Parameter Row Random access memory Read only memory Display scrolling start address parameter Display scrolling length parameter Length, including horizontal blanking, of one screen line Display memory Display drive waveform parameter Windows per screen parameter
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Request for Information on S1D13305 Series Company: The phenomenon occurred on: Device name: S1D13305F00A/ S1D13305F00B Number of units of the device causing the phenomenon: __units (Scope of occurrence: ___ / ___) Your address: Your phone number: FAX: Dated:__________, 19____ Name of the inquiring person: Desired date of receiving the reply: ______________ (Lot No. ) Applications:
Documents in your current possession:
Image plane size: ____ dots x ____ dots (single-plane drive/2-plane drive) Using LCD module (manufacturer): Frame frequency: Hz. ------------------< (1)' > Display mode (circle either one) ---------------------------------------------(1) First layer: Characters Two-part plane, Second layer: Graphics Single plane (2) First layer: Characters Single plane, Second layer: Graphics Single plane (3) First layer: Characters Two-part plane, Second layer: Graphics Two-part plane (4) First layer: Graphics Two-part plane, Second layer: Graphics Single plane (5) First layer: Graphics Single plane, Second layer: Graphics Single plane (6) First layer: Graphics Single plane, Second layer: Graphics Single plane, (7) First layer: Graphics Two-part plane, Second layer: Graphics Two-part plane
< (4)' > Third layer: Graphics Single plane
Initialization parameter: Give in decimals or duodecimals. ----------------------------------------------------------------System setting Scroll HDOT SCR CSRFORM P1(IV, W/S, M2, M1, M0) = P1(SADIL) = P1 = P1 = P2(W/F, FX) = P2(SADIH) = OVLAY P2 = P3(FY) = P3(SL1) = P1 = P4(C/R) = P4(SAD2L) = DISP ON/OFF P5(TC/R) = P5(SAD2H) = P1 = P6(L/F) = P6(SL2) = CSRW P7(APL) = P7(SAD3L) = P1 = P8(APH) = P8(SAD3H) = P2 = P9(SAD4L) = CSR DIR P10(SAD4H) = C = Oscillation frequency: CPU: Frame memory capacity: Kb. MHz. (internal/external) CPU clock: (using memory IC: MHz. , access time: nsec.)
Descriptions of your inquiry (Give details such as what type of display is being sought for and which phenomenon is occurring.)
Attached documents (circuit diagram, timing chart, program list, or others)
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Technical Manual
S1D13305 Series
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
http://www.epson.co.jp/device/
This manual was made with recycle papaer, and printed using soy-based inks.
First issue April,1998 D Printed March, 2001 in Japan C A

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